tag: Kyushu Institute of Technology

Neuromorphic Devices Based On Memristive Nanowire Networks
By Technical Paper Link - 16 Nov, 2023 - Comments: 0

A technical paper titled “Online dynamical learning and sequence memory with neuromorphic nanowire networks” was published by researchers at University of Sydney, University of California Los Angeles (UCLA), National Institute for Materials Science (NIMS), Kyushu Institute of Technology (Kyutech), and University of Sydney Nano Institute. Abstract: "Nanowire Networks (NWNs) belong to an em... » read more

Radiation-Hardened Non-Volatile Magnetic Latch That Tolerates SNUs and DNUs
By Technical Paper Link - 13 Sep, 2022 - Comments: 0

A research paper titled "A Radiation-Hardened Non-Volatile Magnetic Latch with High Reliability and Persistent Storage" was published by researchers at Anhui University, Hefei University of Technology, LIRMM, and Kyutech. According to the abstract: "Based on an advanced triple-path dual-interlocked-storage-cell (TPDICE) and MTJs, this paper proposes a radiation-hardened non-volatile magneti... » read more

Technical Paper Roundup: Sept. 12
By Linda Christensen - 12 Sep, 2022 - Comments: 0

New technical papers added to Semiconductor Engineering’s library this week. [table id=51 /] Semiconductor Engineering is in the process of building this library of research papers. Please send suggestions (via comments section below) for what else you’d like us to incorporate. If you have research papers you are trying to promote, we will review them to see if they are a good fit f... » read more

Robust Latch Hardened Against QNUs for Safety-Critical Applications in 22nm CMOS Technology
By Technical Paper Link - 07 Sep, 2022 - Comments: 0

A technical paper titled "Cost-Optimized and Robust Latch Hardened against Quadruple Node Upsets for Nanoscale CMOS" was just published by researchers at Anhui University, Hefei University of Technology, Anhui Polytechnic University, Kyushu Institute of Technology, and the University of Montpellier/CNRS. Abstract: "With the aggressive reduction of CMOS transistor feature sizes, the soft ... » read more

Testing In Context Gaining Ground
By Jeff Dorsch - 10 Dec, 2019 - Comments: 0

Testing in context is beginning to gain wider appeal as chip complexity increases, and as ICs are deployed in more safety-critical and mission-critical applications. While design in context has been the norm for SoCs for some time, a similar approach in test has been slow going. Cell-aware testing technology was first described a decade ago, and since then its adoption has been modest. But w... » read more

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