tag: Lam Research

Blog Review: Jan. 8
By Jesse Allen - 08 Jan, 2025 - Comments: 0

Cadence's Igor Krause unravels the different Orthogonal Header Content (OHC) types in PCIe 6.0, which work as an extra header for the Transaction Layer Packet (TLP) that incorporates information fields that are needed depending on the TLP type. Siemens EDA's Yunhong Min considers how AI and machine learning are reshaping functional verification workflows from translating specifications to de... » read more

What’s Next For Through-Silicon Vias
By Laura Peters - 06 Jan, 2025 - Comments: 0

From large TSVs for MEMS to nanoTSVs for backside power delivery, cost-effective process flows for these interconnects are essential for making 2.5D and 3D packages more feasible. Through-silicon vias (TSVs) enable shorter interconnect lengths, which reduces chip power consumption and latency to carry signals faster from one device to another or within a device. Advanced packaging technology... » read more

Optimizing New Interconnect Technologies To Support Next-Generation Semiconductor Devices
By Assawer Soussou - 18 Dec, 2024 - Comments: 0

Interconnects are the wiring system that connect together the components of a semiconductor device and permit these components to work together. One of the key metrics of any semiconductor interconnect scheme is the metal pitch size. Metal pitch is the minimum distance between the centers of two horizontal interconnects in a semiconductor. It's a key metric used to measure the progress of chip ... » read more

Baby Steps Toward 3D DRAM
By Bryon Moyer - 17 Dec, 2024 - Comments: 0

Flash memory has made incredible capacity strides thanks to monolithic 3D processing enabled by the stacking of more than 200 layers, which is on its way to 1.000 layers in future generations.[1] But the equally important DRAM has achieved a similar manufacturable 3D architecture. The need for a sufficiently large means of storing charge — such as a capacitor — has proved elusive. Severa... » read more

Navigating Increased Complexity In Advanced Packaging
By Gregory Haley - 17 Dec, 2024 - Comments: 1

As chips evolve toward stacked, heterogeneous assemblies and adopt more complex materials, engineers are grappling with new and often less predictable sources of variation. This is redefining what it means to achieve precision, forcing companies to rethink everything from process control and in-line metrology to materials selection and multi-level testing. These assemblies are the result of ... » read more

Chip Industry Week In Review
By The SE Staff - 13 Dec, 2024 - Comments: 0

The 2024 IEEE International Electron Devices Meeting (IEDM) was held this week, prompting a number of announcements from: imec: Proposed a new CFET-based standard cell architecture for the A7 node containing two rows of CFETs with a shared signal routing wall in between, allowing standard cell heights to be reduced from 4 to 3.5T, compared to single-row CFETs. Integrated indium pho... » read more

NAND Flash Targets 1,000 Layers
By Bryon Moyer - 04 Dec, 2024 - Comments: 0

The chip industry is pushing to quadruple the stack height of 3D NAND flash from 200 layers to 800 layers or more over the next few years, using the additional capacity will help to feed the unending need for more memory of all types. Those additional layers will add new reliability issues a number of incremental reliability challenges, but the NAND flash industry has been steadily increasin... » read more

HBM Options Increase As AI Demand Soars
By Laura Peters - 21 Nov, 2024 - Comments: 0

High-bandwidth memory (HBM) sales are spiking as the amount of data that needs to be processed quickly by state-of-the-art AI accelerators, graphic processing units, and high-performance computing applications continues to explode. HBM inventories are sold out, driven by massive efforts and investments in developing and improving large language models such as ChatGPT. HBM is the memory of ch... » read more

Using Dummy Patterning To Solve Etch Uniformity Problems
By James Kim - 21 Nov, 2024 - Comments: 0

Semiconductor devices are made up of hundreds of thin layers of materials stacked by multiple deposition and etch processes. Process engineers need to design the best combination of deposition and etch processes to ensure uniformity across an entire chip area and across the silicon wafer. Uniformity is the most common and critical parameter that is monitored in semiconductor fabrication, especi... » read more

FOPLP Gains Traction in Advanced Semiconductor Packaging
By Gregory Haley - 21 Nov, 2024 - Comments: 1

Fan-Out Panel-Level Packaging (FOPLP) for advanced nodes, once hindered by manufacturability and yield challenges, is emerging as a promising solution to meet the industry’s demands for higher integration densities and cost efficiency. Traditionally, FOPLP has been a go-to solution for cost-sensitive applications in consumer electronics, IoT devices, and mid-tier automotive systems. Its ab... » read more

← Older posts

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy