Big Changes Ahead For Interposers And Substrates

By Gregory Haley - 24 Mar, 2025 - Comments: 1

Interposers and substrates are undergoing a profound transformation from intermediaries to engineered platforms responsible for power distribution, thermal management, high-density interconnects, and signal integrity in the most advanced computing systems. This shift is being driven by AI, high-performance computing (HPC), and next-generation communications, where the need for heterogeneous ... » read more

Improving DRAM Performance Using Dual Work-Function Metal Gate (DWMG) Structures

By Daebin Yim - 20 Mar, 2025 - Comments: 0

Dynamic Random Access Memory (DRAM) serves as the backbone of modern computing, enabling devices ranging from smartphones to high-performance servers. As the demand accelerates for higher density and lower power consumption in memory devices, innovation in reducing DRAM leakage currents and enhancing performance becomes essential. One significant challenge in scaling DRAM technology is gate-... » read more

What Exactly Are Chiplets And Heterogeneous Integration?

By Bryon Moyer - 20 Mar, 2025 - Comments: 1

The terms “chiplet” and “heterogeneous integration” fill news pages, conference papers, and marketing presentations, and for the most part engineers understand what they're reading. But speakers sometimes stumble during a presentation trying to figure out whether a particular die qualifies as a chiplet, and heterogeneous integration comes in different guises for different people. Both t... » read more

The Rise Of Thin Wafer Processing

By Laura Peters - 20 Mar, 2025 - Comments: 0

The shift from planar SoCs to 3D-ICs and advanced packages requires much thinner wafers in order to improve performance and reduce power, reducing the distance that signals need to travel and the amount of energy needed to drive them. Markets calling for ultrathin wafers are growing. The combined thickness of an HBM module with 12 DRAM dies and a base logic chip is still less than that of a ... » read more

Many Options For EUV Photoresists, No Clear Winner

By Katherine Derbyshire - 20 Mar, 2025 - Comments: 2

In EUV lithography, and especially high-numerical-aperture EUV, balancing tradeoffs between resolution, sensitivity and line-width roughness is becoming increasingly difficult. Lithography patterning using extreme UV exposure depends on a resist mask that can simultaneously meet targets of small feature resolution, high sensitivity to EUV wavelength, and acceptable linewidth roughness. Unfor... » read more

Chip Industry Week In Review

By The SE Staff - 07 Mar, 2025 - Comments: 0

The Malaysian government signed a deal with Arm to kickstart a chip design ecosystem. Until now, Malaysia has focused on packaging and test. Adding chip design represents a major change in focus. The country will pay SoftBank $250 million over 10 years for Arm’s chip design IP and train 10,000 engineers. Global chip sales reached $56 billion in January, up nearly 18% from the same period i... » read more

Chip Industry Week In Review

By The SE Staff - 21 Feb, 2025 - Comments: 0

The EU Commission approved €920 million in German State aid to support Infineon in setting up its Smart Power Fab in Dresden. Total funding for the Dresden site amounts to about €1 billion. PDF Solutions will acquire secureWISE for $130 million to expand the reach of its semiconductor manufacturing data platform, providing secure, remote access monitoring and control. Tariffs, trade, and ... » read more

Interconnects Approach Tipping Point

By Laura Peters - 20 Feb, 2025 - Comments: 0

As leading devices move to next generation nanosheets for logic, their interconnections are getting squeezed past the point where they can deliver low resistance pathways. The 1nm (10Å) node will have 20nm pitch and larger metal lines, but the interconnect stack already consumes a third of device power and accounts for 75% of the chip's RC delay. Changing this dynamic requires a superior co... » read more

Mechanical Stress In Semiconductor Development

By Ivan Chakarov - 20 Feb, 2025 - Comments: 0

With the semiconductor industry moving toward 3D DRAM, 3D logic architectures, and 1000+ layer 3D NAND stacks,1 mechanical failures may become more common. Due to the complexity of these structures, mechanical stress from materials processing has the potential to significantly impact yield. 3D processing techniques (etching, deposition, and related chemistries), as well as material property de... » read more

EUV’s Future Looks Even Brighter

By Gregory Haley - 20 Feb, 2025 - Comments: 1

The rapidly increasing demand for advanced-node chips to support everything-AI is putting pressure on the industry's ability to meet demand. The need for cutting-edge semiconductors is accelerating in applications ranging from hyperscale data centers powering large language models to edge AI in smartphones, IoT devices, and autonomous systems. But manufacturing those chips relies heavily on ... » read more

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Big Changes Ahead For Interposers And Substrates

Improving DRAM Performance Using Dual Work-Function Metal Gate (DWMG) Structures

What Exactly Are Chiplets And Heterogeneous Integration?

The Rise Of Thin Wafer Processing

Many Options For EUV Photoresists, No Clear Winner

Chip Industry Week In Review

Chip Industry Week In Review

Interconnects Approach Tipping Point

Mechanical Stress In Semiconductor Development

EUV’s Future Looks Even Brighter

Trending Articles

What Exactly Are Chiplets And Heterogeneous Integration?

Startup Funding: Q1 2025

Chip Industry Week In Review

Chip Industry Week In Review