tag: Lam Research

Assembly Design Rules Slowly Emerge
By Bryon Moyer - 27 Jan, 2025 - Comments: 0

Process design kits (PDKs) play an essential in ensuring that silicon technology can proceed from one generation to the next in a manner that design tools can keep up with. No such infrastructure has been needed for packaging in the past, but that's beginning to change with advanced packages. Heterogeneous assemblies are still ramping up, but their benefits are attracting new designs. “Chi... » read more

Less Waste, Faster Results: Why Virtual Twins Are Critical To Future Semiconductor R&D
By Wojtek Osowiecki - 23 Jan, 2025 - Comments: 0

By Wojciech (Wojtek) Osowiecki, Martyn Coogans, Saravanapriyan Sriraman, Rakesh Ranjan, Yu (Joe) Lu, and David M. Fried The semiconductor industry has long depended on physical experimentation to achieve the precision needed for advanced chip manufacturing. However, this traditional method comes with significant environmental costs—high energy consumption, material waste, and greenhouse ga... » read more

Global IC Fabs And Facilities Report: 2024
By Liz Allan - 21 Jan, 2025 - Comments: 0

The chip industry made significant capital investments this year to build new fabs and facilities or expand existing premises. A number of sites were dedicated to SiC, GaN, DRAM, HBM, along with packaging and assembly by OSATs, and essential gases, chemicals, and other components. More than a dozen R&D centers were also established for 8-inch wafers, EUV, and advanced packaging. Investments... » read more

Chip Industry Week In Review
By The SE Staff - 17 Jan, 2025 - Comments: 0

GlobalFoundries will create a new center for advanced packaging and testing of U.S.-made essential chips within its New York manufacturing facility. A flurry of announcements on advanced semiconductors and AI rolled out this week as U.S. President Biden wrapped up his term: The Biden-Harris Administration released an Interim Final Rule on Artificial Intelligence Diffusion to strengthen ... » read more

Blog Review: Jan. 8
By Jesse Allen - 08 Jan, 2025 - Comments: 0

Cadence's Igor Krause unravels the different Orthogonal Header Content (OHC) types in PCIe 6.0, which work as an extra header for the Transaction Layer Packet (TLP) that incorporates information fields that are needed depending on the TLP type. Siemens EDA's Yunhong Min considers how AI and machine learning are reshaping functional verification workflows from translating specifications to de... » read more

What’s Next For Through-Silicon Vias
By Laura Peters - 06 Jan, 2025 - Comments: 0

From large TSVs for MEMS to nanoTSVs for backside power delivery, cost-effective process flows for these interconnects are essential for making 2.5D and 3D packages more feasible. Through-silicon vias (TSVs) enable shorter interconnect lengths, which reduces chip power consumption and latency to carry signals faster from one device to another or within a device. Advanced packaging technology... » read more

Optimizing New Interconnect Technologies To Support Next-Generation Semiconductor Devices
By Assawer Soussou - 18 Dec, 2024 - Comments: 0

Interconnects are the wiring system that connect together the components of a semiconductor device and permit these components to work together. One of the key metrics of any semiconductor interconnect scheme is the metal pitch size. Metal pitch is the minimum distance between the centers of two horizontal interconnects in a semiconductor. It's a key metric used to measure the progress of chip ... » read more

Baby Steps Toward 3D DRAM
By Bryon Moyer - 17 Dec, 2024 - Comments: 0

Flash memory has made incredible capacity strides thanks to monolithic 3D processing enabled by the stacking of more than 200 layers, which is on its way to 1.000 layers in future generations.[1] But the equally important DRAM has achieved a similar manufacturable 3D architecture. The need for a sufficiently large means of storing charge — such as a capacitor — has proved elusive. Severa... » read more

Navigating Increased Complexity In Advanced Packaging
By Gregory Haley - 17 Dec, 2024 - Comments: 1

As chips evolve toward stacked, heterogeneous assemblies and adopt more complex materials, engineers are grappling with new and often less predictable sources of variation. This is redefining what it means to achieve precision, forcing companies to rethink everything from process control and in-line metrology to materials selection and multi-level testing. These assemblies are the result of ... » read more

Chip Industry Week In Review
By The SE Staff - 13 Dec, 2024 - Comments: 0

The 2024 IEEE International Electron Devices Meeting (IEDM) was held this week, prompting a number of announcements from: imec: Proposed a new CFET-based standard cell architecture for the A7 node containing two rows of CFETs with a shared signal routing wall in between, allowing standard cell heights to be reduced from 4 to 3.5T, compared to single-row CFETs. Integrated indium pho... » read more

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