Laser-Focused Results: Improving EUV Line Edge Roughness With Ion Beam Etching


Extreme ultraviolet (EUV) lithography exposed resist patterns can exhibit excessive line edge roughness (LER) and line width roughness (LWR) due to random or shot noise. Increasing the EUV exposure dose can reduce LER/LWR, but it also decreases wafer throughput, which is highly undesirable given the EUV tool’s high operating costs. Ion beam etching (IBE) can directionally etch away roug... » read more

Molybdenum: Transforming Semiconductor Manufacturing For Next-Generation Technologies


One trillion semiconductors produced in a single year. A digital foundation powering AI's explosive growth. The next frontier requires chips that are smaller, faster, and exponentially more powerful. A new white paper from Counterpoint Research  reveals how advanced metallization—specifically molybdenum—is becoming a critical enabler for semiconductor manufacturing in this new era. Th... » read more

Blog Review: May 14


Siemens’ Stephen V. Chavez finds that proper PCB high voltage spacing between conductive elements is key to reliability and understanding the principles of clearance (through-air spacing) and creepage (along-surface spacing) is critical. Cadence’s Frank Ferro checks out how the new HBM4 standard boosts bandwidth and addresses key issues in the data center, including the growing size of L... » read more

Chip Industry Week in Review


To listen to the podcast version, click here. TSMC unveiled an unusually detailed roadmap at this week's North America Technology Symposium, including future architectures for 3D-ICs for high-performance computing and small, extremely low-power chips for AR/VR glasses, and two implementations of system-on-wafer. Fig. 1: TSMC's future packaging and stacking roadmap. Source: TSMC The ... » read more

Chip Industry Week In Review


[Podcast version is here.] TSMC said it will produce 30% of its leading-edge chips in Arizona when all six of its fabs are operational, a total investment of $165 billion, Axios reported. In its latest SEC filing, the foundry said it continues to add capacity in Taiwan, Arizona, Japan, and Germany. The Trump administration launched a Section 232 investigation into semiconductors and relat... » read more

The Other Side Of The Wafer: Transistor Channel Stress In Backside Power Delivery Networks


As transistor scaling has moved to the angstrom era (18A, 14A, etc.), the issues of interconnect resistance (IR), IR drop, and power loss are becoming more severe. Traditionally, signal lines and power lines are fabricated on the same side of the wafer as the active device. But fabricating everything on one side of the wafer can create a shortage of space and resources at the interconnect la... » read more

Backside Power Delivery Nears Production


Backside power delivery is being called a game changer — a breakthrough technology and the next great enabler in CMOS scaling. It promises significant PPA advances, including faster switching, lower voltage droop, and reduced power supply noise. And it is poised to deliver these benefits below the 2nm node, despite a substantial disruption in front-end processes from lithography pattern di... » read more

Packaging With Fewer People And Better Results


Advanced packaging has evolved far beyond the simple stacking of dies and connecting of interposers. Once a passive conduit between silicon and the outside world, it has become an active component of overall device performance. In today’s multi-die assemblies, the assembly and packaging lines are expected to maintain signal integrity at multi-gigahertz frequencies, manage heat in verticall... » read more

Big Changes Ahead For Interposers And Substrates


Interposers and substrates are undergoing a profound transformation from intermediaries to engineered platforms responsible for power distribution, thermal management, high-density interconnects, and signal integrity in the most advanced computing systems. This shift is being driven by AI, high-performance computing (HPC), and next-generation communications, where the need for heterogeneous ... » read more

Improving DRAM Performance Using Dual Work-Function Metal Gate (DWMG) Structures


Dynamic Random Access Memory (DRAM) serves as the backbone of modern computing, enabling devices ranging from smartphones to high-performance servers. As the demand accelerates for higher density and lower power consumption in memory devices, innovation in reducing DRAM leakage currents and enhancing performance becomes essential. One significant challenge in scaling DRAM technology is gate-... » read more

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