Chip Industry Week In Review

By The SE Staff - 24 Apr, 2026 - Comments: 0

Deals Marvell acquired Polariton Technologies, a Swiss developer of plasmonics-based silicon photonics devices. Onto Innovation is partnering with Rigaku, combining Onto’s analysis software with Rigaku’s CD-SAXS platform for advanced semiconductor process control. Onto also agreed to acquire a 27% stake in Rigaku for about $710M. Tesla plans to use Intel’s 14A process for its T... » read more

TSV Complexity Leads To Manufacturing Bottleneck

By Laura Peters - 22 Apr, 2026 - Comments: 1

Key Takeaways: Through-silicon vias are the biggest enabler of 3D chip stacking and chip-to-PCB connections through silicon interposers. The AI boom is causing HBM and advanced assembly shortages, straining the supply chain. Optimization around etch, fill and reveal help reduce TSV cost. Through-silicon vias (TSVs) provide essential interconnects between DRAM dies inside hig... » read more

Chip Industry Week In Review

By The SE Staff - 17 Apr, 2026 - Comments: 0

Acquisitions and business pivots Teradyne acquired Israel-based TestInsight, a semiconductor test provider with pattern conversion, validation, and virtual test capabilities. Credo plans to acquire DustPhotonics, a developer of silicon photonics PICs for optical transceivers. Molex plans to acquire Teramount, a provider of detachable, passive-alignment fiber-to-chip connectivity solu... » read more

Panel-Level Packaging’s Second Wave Meets Engineering Reality

By Gregory Haley - 16 Apr, 2026 - Comments: 0

Key Takeaways Panel-level packaging is arriving not because the engineering is ready, but because wafer-level economics are breaking down. Glass improves the warpage and dimensional stability problems of organic substrates but introduces a different class of failure modes that require materials solutions, not process adjustments. The central challenges of panel-level processing are m... » read more

Unraveling DRAM SAQP Process Complexity With Monte Carlo Virtual Fabrication

By Swapnil Kailash More - 16 Apr, 2026 - Comments: 0

By Swapnil Kailash More and Roopa Hegde As DRAM technologies scale to increasingly tighter pitches, the patterning requirements exceed the limits of conventional single-exposure DUV lithography. In advanced nodes such as D1b (1-beta), active-area (AA) pitches fall in the range of 22 to 26 nm, well below the capability of single patterning. To achieve these sub-lithographic dimensions, advan... » read more

Challenges In Scaling Chips To 2nm And Below

By Ed Sperling - 30 Mar, 2026 - Comments: 0

Key Takeaways Scaling to 2nm and below continues due to power improvements per watt, but progress is much more challenging and costly. Solutions to problems often create other problems due to less margin for tradeoffs, often requiring larger interposers, more chiplets, and more complex packages. New levels of precision are required throughout the design-through-manufacturing flow, re... » read more

Process Model Precision: Calibrating For Accurate Predictions Of FinFET Device Profiles

By Brett Lowe - 19 Mar, 2026 - Comments: 0

In modern semiconductor process integration, rapid and well-informed path finding is essential for on-time product release. Virtual Design of Engineering (DOE) and predictive modeling can expose integration risks early; however, their value depends on accurate process models calibrated to real fab behavior.1 Reliable prediction requires strong correlations between model inputs and measurable... » read more

Chip Industry Week In Review

By The SE Staff - 13 Mar, 2026 - Comments: 0

Disruptions caused by the Iran conflict have taken about one third of the global helium supply off the market, an essential gas for semiconductor manufacturing, reports the World Economic Forum. Other potential impacts for the chip industry include bromine and other chemical shortages, logistical disruptions, and higher energy prices incurred by fabs in Asia. Top Deals IBM and Lam R... » read more

Chip Industry Week In Review

By The SE Staff - 06 Mar, 2026 - Comments: 0

Think tank IAPS' report on AI integrity attacks contends that advanced AI systems must be protected from hidden tampering, backdoors, or unauthorized changes that could alter their behavior or outputs, especially when AI adoption is scaling rapidly, with over 60% of the federal workforce now using AI every day. Geopolitics The U.S. government has drafted new export rules that may give W... » read more

Blog Review: Mar. 4

By Jesse Allen - 04 Mar, 2026 - Comments: 0

Cadence's Subash Peddu digs into the challenge of balancing performance, power efficiency, SoC layout optimization, and futureproofing when defining SoCs and memory subsystems for tomorrow’s AI accelerators. Siemens' Nicolae Tusinschi suggests that formal verification isn't just about finding bugs, and the ability to achieve mathematical certainty can fundamentally change how hardware desi... » read more

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tag: Lam Research

Chip Industry Week In Review

TSV Complexity Leads To Manufacturing Bottleneck

Chip Industry Week In Review

Panel-Level Packaging’s Second Wave Meets Engineering Reality

Unraveling DRAM SAQP Process Complexity With Monte Carlo Virtual Fabrication

Challenges In Scaling Chips To 2nm And Below

Process Model Precision: Calibrating For Accurate Predictions Of FinFET Device Profiles

Chip Industry Week In Review

Chip Industry Week In Review

Blog Review: Mar. 4

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