One Chip Vs. Many Chiplets

By Ed Sperling - 20 Nov, 2024 - Comments: 1

Experts at the Table: Semiconductor Engineering sat down to discuss the growing list of challenges at advanced nodes and in advanced packages, with Jamie Schaeffer, vice president of product management at GlobalFoundries; Dechao Guo, director of advanced logic technology R&D at IBM; Dave Thompson, vice president at Intel; Mustafa Badaroglu, principal engineer at Qualcomm; and Thomas Ponnusw... » read more

Asia Government Funding Surges

By Liz Allan - 18 Nov, 2024 - Comments: 0

Billions of dollars have been pouring into Asian countries for the past few years in an effort to boost their production capacity, explore leading-edge technology, compete on the global stage, and shore up supply chains in the face of geopolitical turmoil. Each country has its own plan to maintain a foothold in the global market, from China’s Big Fund to Korea’s Yongin Cluster and Japan�... » read more

Chip Industry Week In Review

By The SE Staff - 25 Oct, 2024 - Comments: 0

Europe's top court ruled in Intel's favor, voiding a $1.1 billion fine imposed by the European Union and dismissing charges of anti-competitive behavior. IBM released yield benchmarks for high-NA EUV, which serve as proof points that the newest advanced litho equipment will enable scaling beyond the 2nm process node. Also on the lithography front, Nikon is developing a maskless digital litho... » read more

Metal-Oxide-Metal Capacitor Simulation And Modeling By Virtual Fabrication

By Qingpeng Wang - 24 Oct, 2024 - Comments: 0

Metal-Oxide-Metal (MOM) capacitors are passive radio frequency (RF) capacitive devices that are a common component in semiconductor logic chips [1]. A SPICE model of a MOM capacitor is typically used by designers during the design and performance evaluation of logic chip RF circuitry. Traditionally, it may take at least 3 months from the completion of the design layout, wafer fabrication, final... » read more

Advanced Packaging Driving New Collaboration Across Supply Chain

By Gregory Haley - 24 Oct, 2024 - Comments: 0

The semiconductor industry is undergoing a profound shift in packaging technologies to ones that rely on close collaboration among multiple stakeholders to solve intricate, multi-faceted, and extraordinarily complex problems. At the heart of this change is the convergence of heterogeneous integration, chiplets, and 3D stacking. Heterogeneous approaches allow companies to combine different te... » read more

Monolithic Vs. Heterogeneous Integration

By Ed Sperling - 24 Oct, 2024 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss two very different paths forward for semiconductors and what's needed for each, with Jamie Schaeffer, vice president of product management at GlobalFoundries; Dechao Guo, director of advanced logic technology R&D at IBM; Dave Thompson, vice president at Intel; Mustafa Badaroglu, principal engineer at Qualcomm; and Thomas Po... » read more

Optimizing Wafer Edge Processes For Chip Stacking

By Laura Peters - 23 Sep, 2024 - Comments: 0

Stacking chiplets vertically using short and direct wafer-to-wafer bonds can reduce signal delay to negligible levels, enabling smaller, thinner packages with faster memory/processor speeds and lower power consumption. The race is on to implement wafer stacking and die-to-wafer hybrid bonding, now considered essential for stacking logic and memory, 3D NAND, and possibly multi-layer DRAM stac... » read more

Chip Industry Week In Review

By The SE Staff - 20 Sep, 2024 - Comments: 0

Synopsys agreed to sell its Optical Solutions Group to Keysight for an undisclosed amount, in a deal deemed necessary for Synopsys to win regulatory approval for its planned acquisition of Ansys. The sale to Keysight is contingent on the Synopsys-Ansys deal going through. Meanwhile, Ansys has its own optical business. The U.S. Department of Defense (DoD) made the first awards for Microelectr... » read more

Reducing Transistor Capacitance At The 5nm Node Using A Source/Drain Contact Recess

By Pradeep Nanja - 19 Sep, 2024 - Comments: 0

In logic devices such as FinFETs (field-effect transistors), metal gate parasitic capacitance can negatively impact electrical performance. One potential way to reduce this parasitic capacitance is to add a source/drain contact (CT) recess step when building the source/drain metal structure. However, this additional structure can potentially increase the source/drain to via resistance. Using... » read more

New Materials Are in High Demand

By Bryon Moyer - 19 Sep, 2024 - Comments: 0

Materials suppliers are responding to the intense pressures to improve power, performance, scaling, and cost issues, which follows a long timeline from synthesis to development and high volume manufacturing in fabs. The advances in machine learning help present a wide field of candidates, which engineers then narrow to potential use. When building standard logic semiconductor chips, the prim... » read more

← Older posts Newer posts →

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

NAND Flash Targets 1,000 Layers

New techniques go beyond improved deposition and etching, but challenges stack up, too.

by Bryon Moyer

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

tag: Lam Research

One Chip Vs. Many Chiplets

Asia Government Funding Surges

Chip Industry Week In Review

Metal-Oxide-Metal Capacitor Simulation And Modeling By Virtual Fabrication

Advanced Packaging Driving New Collaboration Across Supply Chain

Monolithic Vs. Heterogeneous Integration

Optimizing Wafer Edge Processes For Chip Stacking

Chip Industry Week In Review

Reducing Transistor Capacitance At The 5nm Node Using A Source/Drain Contact Recess

New Materials Are in High Demand

Trending Articles

Baby Steps Toward 3D DRAM

What’s Next For Through-Silicon Vias

Chip Industry Week in Review

Strain, Stress In Advanced Packages Drives New Design Approaches

Navigating Increased Complexity In Advanced Packaging

Knowledge Centers
Entities, people and technologies explored