Chip Industry Week In Review

By The SE Staff - 14 Feb, 2025 - Comments: 0

Worldwide silicon wafer shipments declined nearly 2.7% to 12,266 million square inches in 2024, with wafer revenue contracting 6.5% to $11.5 billion, according to the SEMI Silicon Manufacturers Group. CSIS released a new report, “Critical Minerals and the Future of the U.S. Economy,” with detailed analysis and policy recommendations for building a secure mineral supply chain for semicond... » read more

Research Bits: Feb. 10

By Jesse Allen - 10 Feb, 2025 - Comments: 0

Speeding up 3D NAND etch Researchers from Lam Research, the University of Colorado Boulder, and Princeton Plasma Physics Laboratory (PPPL) investigated ways to speed up the cryogenic reactive ion etching process for 3D NAND by using a combined hydrogen fluoride gas to create the plasma. “Cryo etch with the hydrogen fluoride plasma showed a significant increase in the etching rate compared... » read more

Chip Industry Week In Review

By The SE Staff - 31 Jan, 2025 - Comments: 0

Chinese startup DeepSeek rattled the tech world and U.S. stock market with claims it spent just $5.6 million on compute power for its AI model compared to its billion-dollar rivals in the U.S. The announcement raised questions about U.S. investment strategies in AI infrastructure and led to an initial $600 billion selloff of NVIDIA stock. Since its launch, DeepSeek reportedly was hit by malicio... » read more

Assembly Design Rules Slowly Emerge

By Bryon Moyer - 27 Jan, 2025 - Comments: 0

Process design kits (PDKs) play an essential in ensuring that silicon technology can proceed from one generation to the next in a manner that design tools can keep up with. No such infrastructure has been needed for packaging in the past, but that's beginning to change with advanced packages. Heterogeneous assemblies are still ramping up, but their benefits are attracting new designs. “Chi... » read more

Less Waste, Faster Results: Why Virtual Twins Are Critical To Future Semiconductor R&D

By Wojtek Osowiecki - 23 Jan, 2025 - Comments: 0

By Wojciech (Wojtek) Osowiecki, Martyn Coogans, Saravanapriyan Sriraman, Rakesh Ranjan, Yu (Joe) Lu, and David M. Fried The semiconductor industry has long depended on physical experimentation to achieve the precision needed for advanced chip manufacturing. However, this traditional method comes with significant environmental costs—high energy consumption, material waste, and greenhouse ga... » read more

Global IC Fabs And Facilities Report: 2024

By Liz Allan - 21 Jan, 2025 - Comments: 0

The chip industry made significant capital investments this year to build new fabs and facilities or expand existing premises. A number of sites were dedicated to SiC, GaN, DRAM, HBM, along with packaging and assembly by OSATs, and essential gases, chemicals, and other components. More than a dozen R&D centers were also established for 8-inch wafers, EUV, and advanced packaging. Investments... » read more

Chip Industry Week In Review

By The SE Staff - 17 Jan, 2025 - Comments: 0

GlobalFoundries will create a new center for advanced packaging and testing of U.S.-made essential chips within its New York manufacturing facility. A flurry of announcements on advanced semiconductors and AI rolled out this week as U.S. President Biden wrapped up his term: The Biden-Harris Administration released an Interim Final Rule on Artificial Intelligence Diffusion to strengthen ... » read more

Blog Review: Jan. 8

By Jesse Allen - 08 Jan, 2025 - Comments: 0

Cadence's Igor Krause unravels the different Orthogonal Header Content (OHC) types in PCIe 6.0, which work as an extra header for the Transaction Layer Packet (TLP) that incorporates information fields that are needed depending on the TLP type. Siemens EDA's Yunhong Min considers how AI and machine learning are reshaping functional verification workflows from translating specifications to de... » read more

What’s Next For Through-Silicon Vias

By Laura Peters - 06 Jan, 2025 - Comments: 0

From large TSVs for MEMS to nanoTSVs for backside power delivery, cost-effective process flows for these interconnects are essential for making 2.5D and 3D packages more feasible. Through-silicon vias (TSVs) enable shorter interconnect lengths, which reduces chip power consumption and latency to carry signals faster from one device to another or within a device. Advanced packaging technology... » read more

Optimizing New Interconnect Technologies To Support Next-Generation Semiconductor Devices

By Assawer Soussou - 18 Dec, 2024 - Comments: 0

Interconnects are the wiring system that connect together the components of a semiconductor device and permit these components to work together. One of the key metrics of any semiconductor interconnect scheme is the metal pitch size. Metal pitch is the minimum distance between the centers of two horizontal interconnects in a semiconductor. It's a key metric used to measure the progress of chip ... » read more

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tag: Lam Research

Chip Industry Week In Review

Research Bits: Feb. 10

Chip Industry Week In Review

Assembly Design Rules Slowly Emerge

Less Waste, Faster Results: Why Virtual Twins Are Critical To Future Semiconductor R&D

Global IC Fabs And Facilities Report: 2024

Chip Industry Week In Review

Blog Review: Jan. 8

What’s Next For Through-Silicon Vias

Optimizing New Interconnect Technologies To Support Next-Generation Semiconductor Devices

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