tag: languages

The Next Incarnation Of EDA
By Brian Bailey - 25 Aug, 2022 - Comments: 0

The EDA industry has incrementally addressed issues as they arise in the design of electronic systems, but is there about to be a disruption? Academia is certainly seeing that as a possibility, but not all of them see it happening for the same reason. The academic community questioned the future of EDA at the recent Design Automation Conference. Rather than EDA as we know it going away, they... » read more

Who Does Processor Validation?
By Brian Bailey - 27 Jun, 2022 - Comments: 1

Defining what a processor is, and what it is supposed to do, is not always as easy as it sounds. In fact, companies are struggling with the implications of hundreds of heterogenous processing elements crammed into a single chip or package. Companies have extensive verification methodologies, but not for validation. Verification is a process of ensuring that an implementation matches a specif... » read more

ASIC/IC Verification Trends With A Focus On Factors Of Silicon Success
By Harry Foster - 08 Jul, 2021 - Comments: 0

At long last we come to the final installment of our four-part series presenting the findings of the Wilson Research Group Functional Verification 2020 study. In this article we discuss verification trends in IC/ASIC language and library adoption, low power management, and verification effectiveness. We then take a deeper dive into two somewhat surprising phenomena revealed in the data: the ... » read more

A Price To Be Paid
By Brian Bailey - 27 May, 2021 - Comments: 1

Ancient wisdom says you should be careful what you ask for, because you just might get it. This was certainly true many times during my career within EDA, and I am sure it is still happening today. Sometimes the outcome was not what was wanted, or the price was higher than expected. As an example, consider VHDL, the language that was meant to correct the problems of Verilog. One of the probl... » read more

Clarifying Language/Methodology Confusion
By Aldec - 28 Oct, 2020 - Comments: 0

Engineers working on modern, large FPGA designs face multiple challenges: changing languages, methodologies and tools implementing them. The fact that many designs now contain both hardware and software only add to the confusion. This document tries to clarify the situation. Click here to read more. » read more

The Evolution Of High-Level Synthesis
By Brian Bailey - 27 Aug, 2020 - Comments: 3

High-level synthesis is getting yet another chance to shine, this time from new markets and new technology nodes. But it's still unclear how fully this technology will be used. Despite gains, it remains unlikely to replace the incumbent RTL design methodology for most of the chip, as originally expected. Seen as the foundational technology for the next generation of EDA companies around the ... » read more

Universal Verification Methodology Running Out Of Steam
By Ann Mutschler - 30 Jul, 2020 - Comments: 2

For the past decade or so, the Universal Verification Methodology (UVM) has been the de facto verification methodology supported by the entire EDA industry. But as chips become more heterogeneous, more complex, and significantly larger, UVM is running out of steam. Consensus is building that some fundamental changes are required, moving tools up a level of abstraction and making them more ag... » read more

Fusing Implementation And Verification
By Ed Sperling - 02 Mar, 2020 - Comments: 0

Susantha Wijesekara, senior application engineer at Synopsys, drills down into how to re-use Tcl scripts for static verification, what needs to be done with those scripts to make that possible, why that is critical to “shift left,” and how that approach saves time, money, and improves quality. » read more

The Trouble With Semantics
By Brian Bailey - 30 Jan, 2020 - Comments: 2

Semantics are important. They tell us what something means. Without semantics you just have a jumble of syntax. The better defined the semantics are, the less likely something is to be mis-interpreted because they can be more rigidly analyzed. The semantics of the English language are not very well defined, which is why it is impossible to write a specification where everyone agrees upon wha... » read more

High-Level Design And High-Level Verification
By Dominik Strasser - 26 Sep, 2019 - Comments: 0

Not so long ago, some EDA vendors were painting a very attractive picture of chip design in the then-near future. The idea was that an architectural team would write a single description of the complete system in some high-level language, usually C/C++/SystemC, and that a new class of EDA tool would automatically partition the design into hardware and software, choosing the functionality of eac... » read more

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