Metrology And Inspection For The Chiplet Era


New developments and innovations in metrology and inspection will enable chipmakers to identify and address defects faster and with greater accuracy than ever before, all of which will be required at future process nodes and in densely packed assemblies of chiplets. These advances will affect both front-end and back-end processes, providing increased precision and efficiency, combined with a... » read more

Key Technologies To Extend EUV To 14 Angstroms


The top three foundries plan to implement high-NA EUV lithography as early as 2025 for the 18 angstrom generation, but the replacement of single exposure high-NA (0.55) over double patterning with standard EUV (NA = 0.33) depends on whether it provides better results at a reasonable cost per wafer. So far, 2024 has been a banner year for high-numerical aperture EUV lithography. Intel Foundry... » read more

Navigating the Metrology Maze For GAA FETs


The chip industry is pushing the boundaries of innovation with the evolution of finFETs to gate-all-around (GAA) nanosheet transistors at the 3nm node and beyond, but it also is adding significant new metrology challenges. GAA represents a significant advancement in transistor architecture, where the gate material fully encompasses the nanosheet channel. This approach allows for the vertical... » read more

Measuring 3D Sidewall Topography & LER for Photoresist Patterns Using Tip-Tilting AFM Technology


A new technical paper titled "Enhancing the precision of 3D sidewall measurements of photoresist using atomic force microscopy with a tip-tilting technique" by researchers at National Metrology Institute of Japan (NMIJ) and National Institute of Advanced Industrial Science and Technology (AIST). "We have developed a technique for measuring the sidewall of the resist pattern using atomic for... » read more

How Does Line Edge Roughness (LER) Affect Semiconductor Performance At Advanced Nodes?


BEOL metal line RC delay has become a dominant factor that limits chip performance at advanced nodes [1]. Smaller metal line pitches require a narrower line CD and line to line spacing, which introduces higher metal line resistance and line to line capacitance. This is demonstrated in figure 1, which displays a simulation of line resistance vs. line CD across different BEOL metals. Even without... » read more

A Study Of The Impact Of Line Edge Roughness On Metal Line Resistance Using Virtual Fabrication


BEOL metal line RC delay has become a dominant factor limiting chip operation speeds at advanced nodes. This is because smaller metal line pitches require narrower line CD and line-to-line spacing, which introduces higher metal line resistance and line-to-line capacitance. A surface scattering effect is the root cause for the exponentially increased metal resistivity at smaller metal line pitch... » read more

Finding, Predicting EUV Stochastic Defects


Several vendors are rolling out next-generation inspection systems and software that locates problematic defects in chips caused by processes in extreme ultraviolet (EUV) lithography. Each defect detection technology involves various tradeoffs. But it’s imperative to use one or more of them in the fab. Ultimately, these so-called stochastic-induced defects caused by EUV can impact the perf... » read more

Effects Of A Random Process Variation On The Transfer Characteristics Of A Fundamental Photonic Integrated Circuit Component


Silicon photonics is rapidly emerging as a promising technology to enable higher bandwidth, lower energy, and lower latency communication and information processing, and other applications. In silicon photonics, existing CMOS manufacturing infrastructure and techniques are leveraged. However, a key challenge for silicon photonics is the lack of mature models that take into account known CMOS pr... » read more

Analyzing Worst-Case Silicon Photonic Device Performance Through Process Modeling And Optical Simulation


Silicon photonics is an emerging and rapidly-expanding design platform that promises to enable higher-bandwidth communication and other applications. One of the best qualities of silicon photonics is its ability to leverage existing CMOS fabrication equipment and process flows. However, this means that it is subject to the same process defects and variations. Previous blog posts [References 1,2... » read more

Effects of a Random Process Variation on the Transfer Characteristics of a Fundamental Photonic Integrated Circuit Component


Silicon photonics is rapidly emerging as a promising technology to enable higher bandwidth, lower energy, and lower latency communication and information processing, and other applications. In silicon photonics, existing CMOS manufacturing infrastructure and techniques are leveraged. However, a key challenge for silicon photonics is the lack of mature models that take into account known CMOS pr... » read more

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