tag: library characterization

Using AWS Cloud Services For IC Library Characterization That Is Scalable, Secure, And Fast
By Siemens EDA - 10 Feb, 2021 - Comments: 0

Siemens’ AMS Verification team and Amazon Web Services (AWS) have collaborated to provide users with a scalable, secure and cost-effective cloud characterization flow that enables users to leverage cloud computing resources to accelerate library characterization, reduce compute resource bottlenecks, as well as improve characterization runtime predictability. To read more, click here. » read more

Cloud Characterization
By WeiLii Tan - 19 Dec, 2019 - Comments: 0

Library characterization is a compute-intensive task that takes days to weeks to complete. Runtimes for library characterization are increasing due to larger library sizes, higher number of operating conditions to characterize, as well as the need for statistical variation modeling in libraries at 22/20nm and smaller process nodes. Cloud platforms offer a way to accelerate library characterizat... » read more

Improving Library Characterization Quality And Runtime With Machine Learning
By Megan Marsh - 25 Oct, 2018 - Comments: 0

By Megan Marsh and Wei-Lii Tan Today’s semiconductor applications, ranging from advanced sensory applications, IoT, edge computing devices, high performance computing, to dedicated A.I. chips, are constantly pushing the boundaries of attainable power, performance, and area (PPA) metrics. The race to design and ship these innovative devices has resulted in a focused, time-to-market-driven e... » read more

Next-Generation Liberty Verification And Debugging
By WeiLii Tan - 27 Sep, 2018 - Comments: 1

Accurate library characterization is a crucial step for modern chip design and verification. For full-chip designs with billions of transistors, timing sign-off through simulation is unfeasible due to run-time and memory constraints. Instead, a scalable methodology using static timing analysis (STA) is required. This methodology uses the Liberty file to encapsulate library characteristics such ... » read more

Addressing Process Variation And Reducing Timing Pessimism At 16nm And Below
By Cadence - 13 Jul, 2016 - Comments: 0

At 16nm and below, on-chip variation (OCV) becomes a critically important issue. Increasing process variation makes a larger impact on timing, which becomes more pronounced in low-power designs with ultra-low voltage operating conditions. In this paper, we will discuss how a new methodology involving more accurate library characterization and variation modeling can reduce timing margins in libr... » read more

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