Reduce Augmented Reality Device Time-to-Market by Bringing Manufacturing Impact to Optical Simulation

By Synopsys - 24 Oct, 2024 - Comments: 0

Disruptive AR systems will push the limits of optics: limits in design, limits in manufacturing, and limits in overall system integration. The trend of optical components being integrated into more complex miniaturized systems is impacting optical software. Optical design software has been around for decades to design, simulate, and analyze any optical component from lenses and mirrors to light... » read more

Metrology And Inspection For The Chiplet Era

By Gregory Haley - 06 Aug, 2024 - Comments: 0

New developments and innovations in metrology and inspection will enable chipmakers to identify and address defects faster and with greater accuracy than ever before, all of which will be required at future process nodes and in densely packed assemblies of chiplets. These advances will affect both front-end and back-end processes, providing increased precision and efficiency, combined with a... » read more

Improving Line Edge Roughness Using Virtual Fabrication

By Qingpeng Wang - 23 Jul, 2024 - Comments: 0

Line edge roughness (LER) is a variation in the width of a lithographic pattern along one edge of a structure inside a chip. Line edge roughness can be a critical variation source and defect mechanism in advanced logic and memory devices and can lead to poor device performance or even device failure. [1~3]. Deposition-etch cycling is an effective technique to reduce line edge roughness. In this... » read more

Nanoimprint Finally Finds Its Footing

By Gregory Haley - 20 Apr, 2023 - Comments: 2

Nanoimprint lithography, which for decades has trailed behind traditional optical lithography, is emerging as the technology of choice for the rapidly growing photonics and biotech chips markets. First introduced in the mid-1990s, nanoimprint lithography (NIL) has consistently been touted as a lower-cost alternative to traditional optical lithography. Even today, NIL potentially is capable o... » read more

Challenges Grow For CD-SEMs At 5nm And Beyond

By Gregory Haley - 11 Apr, 2023 - Comments: 1

CD-SEM, the workhorse metrology tool used by fabs for process control, is facing big challenges at 5nm and below. Traditionally, CD-SEM imaging has relied on a limited number of image frames for averaging, which is necessary both to maintain throughput speeds and to minimize sample damage from the electron beam itself. As dimensions get smaller, these limitations result in higher levels of n... » read more

Measuring 3D Sidewall Topography & LER for Photoresist Patterns Using Tip-Tilting AFM Technology

By Technical Paper Link - 19 Feb, 2023 - Comments: 0

A new technical paper titled "Enhancing the precision of 3D sidewall measurements of photoresist using atomic force microscopy with a tip-tilting technique" by researchers at National Metrology Institute of Japan (NMIJ) and National Institute of Advanced Industrial Science and Technology (AIST). "We have developed a technique for measuring the sidewall of the resist pattern using atomic for... » read more

Looking Forward To SPIE, And Beyond

By Katherine Derbyshire - 16 Feb, 2023 - Comments: 0

On the eve of this year’s SPIE Advanced Lithography + Patterning conference, I took a look at the IEEE Devices and Systems Roadmap’s lithography section. It’s especially notable for the emergence of EUV lithography, which has quickly become critical for advanced logic. High-NA tools to support still smaller dimensions are on the horizon. In the near-term, though, the key challenge is not ... » read more

How Does Line Edge Roughness (LER) Affect Semiconductor Performance At Advanced Nodes?

By Yu De Chen - 26 Sep, 2022 - Comments: 0

BEOL metal line RC delay has become a dominant factor that limits chip performance at advanced nodes [1]. Smaller metal line pitches require a narrower line CD and line to line spacing, which introduces higher metal line resistance and line to line capacitance. This is demonstrated in figure 1, which displays a simulation of line resistance vs. line CD across different BEOL metals. Even without... » read more

A Study Of The Impact Of Line Edge Roughness On Metal Line Resistance Using Virtual Fabrication

By Coventor - 15 Sep, 2022 - Comments: 0

BEOL metal line RC delay has become a dominant factor limiting chip operation speeds at advanced nodes. This is because smaller metal line pitches require narrower line CD and line-to-line spacing, which introduces higher metal line resistance and line-to-line capacitance. A surface scattering effect is the root cause for the exponentially increased metal resistivity at smaller metal line pitch... » read more

Advantages Of Measuring Surface Roughness With White Light Interferometry

By Bruker - 09 Aug, 2022 - Comments: 0

The concept of measuring surface roughness originated nearly a century ago as a means to prevent uncertainty and disputes between manufacturers and buyers. Now, it has become a common identifier used throughout industry for validating manufacturing processes, confirming adherence to both internal and regulatory specifications, and guaranteeing quality and performance of end products. Subjective... » read more

← Older posts

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: line-edge roughness