tag: LLMs

Generating And Evaluating HW Verification Assertions From Design Specifications Via Multi-LLMs
By Technical Paper Link - 06 Feb, 2024 - Comments: 0

A technical paper titled “AssertLLM: Generating and Evaluating Hardware Verification Assertions from Design Specifications via Multi-LLMs” was published by researchers at Hong Kong University of Science and Technology. Abstract: "Assertion-based verification (ABV) is a critical method for ensuring design circuits comply with their architectural specifications, which are typically describe... » read more

Training Large LLM Models With Billions To Trillion Parameters On ORNL’s Frontier Supercomputer
By Technical Paper Link - 16 Jan, 2024 - Comments: 0

A technical paper titled “Optimizing Distributed Training on Frontier for Large Language Models” was published by researchers at Oak Ridge National Laboratory (ORNL) and Universite Paris-Saclay. Abstract: "Large language models (LLMs) have demonstrated remarkable success as foundational models, benefiting various downstream applications through fine-tuning. Recent studies on loss scaling ... » read more

Unlocking The Power Of Edge Computing With Large Language Models
By Paul Karazuba - 30 Oct, 2023 - Comments: 0

In recent years, Large Language Models (LLMs) have revolutionized the field of artificial intelligence, transforming how we interact with devices and the possibilities of what machines can achieve. These models have demonstrated remarkable natural language understanding and generation abilities, making them indispensable for various applications. However, LLMs are incredibly resource-intensi... » read more

A Study Of LLMs On Multiple AI Accelerators And GPUs With A Performance Evaluation
By Technical Paper Link - 19 Oct, 2023 - Comments: 0

A technical paper titled “A Comprehensive Performance Study of Large Language Models on Novel AI Accelerators” was published by researchers at Argonne National Laboratory, State University of New York, and University of Illinois. Abstract: "Artificial intelligence (AI) methods have become critical in scientific applications to help accelerate scientific discovery. Large language models (L... » read more

LLMs For Hardware Design Verification
By Technical Paper Link - 16 Oct, 2023 - Comments: 0

A technical paper titled “LLM4DV: Using Large Language Models for Hardware Test Stimuli Generation” was published by researchers at University of Cambridge, lowRISC, and Imperial College London. Abstract: "Test stimuli generation has been a crucial but labor-intensive task in hardware design verification. In this paper, we revolutionize this process by harnessing the power of large langua... » read more

LLM-Aided AI Accelerator Design Automation (Georgia Tech)
By Technical Paper Link - 28 Sep, 2023 - Comments: 0

A technical paper titled “GPT4AIGChip: Towards Next-Generation AI Accelerator Design Automation via Large Language Models” was published by researchers at Georgia Institute of Technology. Abstract: "The remarkable capabilities and intricate nature of Artificial Intelligence (AI) have dramatically escalated the imperative for specialized AI accelerators. Nonetheless, designing these accele... » read more

LLM-Assisted Generation Of Formal Verification Testbenches: RTL to SVA (Princeton)
By Technical Paper Link - 28 Sep, 2023 - Comments: 0

A technical paper titled “From RTL to SVA: LLM-assisted generation of Formal Verification Testbenches” was published by researchers at Princeton University. Abstract: "Formal property verification (FPV) has existed for decades and has been shown to be effective at finding intricate RTL bugs. However, formal properties, such as those written as System Verilog Assertions (SVA), are time-con... » read more

Issues and Opportunities in Using LLMs for Hardware Design
By Technical Paper Link - 01 Jun, 2023 - Comments: 0

A technical paper titled "Chip-Chat: Challenges and Opportunities in Conversational Hardware Design" was published by researchers at NYU and University of New South Wales. Abstract "Modern hardware design starts with specifications provided in natural language. These are then translated by hardware engineers into appropriate Hardware Description Languages (HDLs) such as Verilog before syn... » read more

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