tag: low-power design

Security Power Requirements Are Growing
By Adam Kovac - 28 Apr, 2025 - Comments: 0

Determining how much power to budget for security in a chip design is a complex calculation. It starts with a risk assessment of the cost of a breach and the number of possible attack vectors, and whether security is active or passive. Different forms of root of trust and cryptography have different power costs. Different systems could require tradeoffs between performance and security, whic... » read more

Leveraging Foundation IP For Low-Power AI Processor Development
By Shruti Bagaria - 15 Apr, 2025 - Comments: 0

Artificial intelligence (AI) has become widespread in recent years, quickly establishing itself as a groundbreaking technology. AI operates on machine learning (ML) algorithms, which demand substantial computational power. Traditionally, designers have utilized graphics processing units (GPUs) to run these ML algorithms. Initially created for graphics rendering, GPUs have shown to be highly eff... » read more

Optimizing Data Movement In SoCs And Advanced Packages
By Ed Sperling - 18 Mar, 2025 - Comments: 0

The amount of data that needs to move around a chip is growing exponentially, driven by the rollout of AI and more sensors everywhere. There may be hundreds of IP blocks, more compute elements, and many more wires to contend with. Andy Nightingale, vice president of product management and marketing at Arteris, talks about the demand for low-latency on-chip communication in increasingly complex ... » read more

The Road To Super Chips
By Ed Sperling - 27 Jan, 2025 - Comments: 0

Reticle size limitations are forcing chip design teams to look beyond a single SoC or processor in order to achieve orders of magnitude improvements in processing that are required for AI. But moving data between more processing elements adds a whole new set of challenges that need to be addressed at multiple levels. Steve Woo, distinguished inventor and fellow at Rambus, examines the benefits ... » read more

Impact of Extremely Low Temperatures On The 5nm SRAM Array Size and Performance
By Technical Paper Link - 20 Jan, 2025 - Comments: 0

A new technical paper titled "Novel Trade-offs in 5 nm FinFET SRAM Arrays at Extremely Low Temperatures" was published by researchers at University of Stuttgart, IIT Kanpur, National Yang Ming Chiao Tung University, Khalifa University, and TU Munich. Abstract "Complementary metal–oxide–semiconductor (CMOS)-based computing promises drastic improvement in performance at extremely low temp... » read more

Power Budgets Optimized By Managing Glitch Power
By Adam Kovac - 16 Jan, 2025 - Comments: 0

“Waste not, want not,” says the old adage, and in general, that’s good advice to live by. But in the realm of chip design, wasting power is a fact of physics. Glitch power – power that gets expended due to delays in gates and/or wires – can account for up to 40% of the power budget in advanced applications like data center servers. Even in less high-powered circuits, such as those fou... » read more

How Big A Deal Is Aging?
By Brian Bailey - 17 Oct, 2024 - Comments: 0

Nothing lasts forever, but in the semiconductor world things used to last long enough to become obsolete long before their end of life. That's no longer the case with newer nodes, and it is raising concerns in safety-critical markets such as automotive. Being able to fully understand what happens inside of chips is still a work in progress, and analysis approaches are trying to keep up. Unti... » read more

Higher Density, More Data Create New Bottlenecks In AI Chips
By Adam Kovac - 12 Sep, 2024 - Comments: 0

Data movement is becoming a bigger problem at advanced nodes and in advanced packaging due to denser circuitry, more physical effects that can affect the integrity of signals or the devices themselves, and a significant increase in data from AI and machine learning. Just shrinking features in a design is no longer sufficient, given the scaling mismatch between SRAM-based L1 cache and digital... » read more

Where Power Savings Really Count
By Ed Sperling - 31 Jul, 2024 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss why and where improvements in architectures and data movement will have the biggest impact, with Hans Yeager, senior principal engineer, architecture, at Tenstorrent; Joe Davis, senior director for Calibre interfaces and EM/IR product management at Siemens EDA; Mo Faisal, CEO of Movellus; Trey Roessig, CTO and senior vice presi... » read more

New Approaches Needed For Power Management
By Karen Heyman - 13 Jun, 2024 - Comments: 0

Power is becoming a bigger concern as the amount of data being processed continues to grow, forcing chipmakers and systems companies to rethink compute architectures from the end point all the way to the data center. There is no simple fix to this problem. More data is being collected, moved, and processed, requiring more power at every step, and more attention to physical effects such as he... » read more

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