tag: low-power design

Tech Talk: 7nm Process Variation
By Ed Sperling - 17 Jan, 2018 - Comments: 0

Ankur Gupta, director of field applications at ANSYS, discusses process variation and the problems it can cause at 10/7nm and beyond. https://youtu.be/WHNjFr1Da6s » read more

PowerDown: Power Efficiency
By Kevin Fogarty - 15 Jan, 2018 - Comments: 0

Power Down Semiconductor wants to make the batteries in smartphones and IoT devices last 10 times longer by not wasting power they’ve already used. Every time an intelligent device has a thought, it pulls power from a battery and sends it through its maze of wires and millions of gates to create a O or a 1 at key points in the control and logic circuits. “Think about how much energy... » read more

Turning Down The Power
By Jeff Dorsch - 11 Jan, 2018 - Comments: 0

Chip and system designers are giving greater weight to power issues these days. But will they inevitably hit a wall in accounting for ultra-low-power considerations? Performance, power, and area are the traditional attributes in chip design. Area was originally the main priority, with feature sizes constantly shrinking according to Moore's Law. Performance was in the saddle for many years. M... » read more

Could Liquid IP Lead To Better Chips? (Part 3)
By Brian Bailey - 09 Jan, 2018 - Comments: 0

Semiconductor Engineering sat down to discuss the benefits that could come from making IP available as abstract blocks instead of RTL implementations with Mark Johnstone, technical director for Electronic Design Automation for [getentity id="22499" e_name="NXP"] Semiconductor; [getperson id="11489" p_name="Drew Wingard"], CTO at [getentity id="22605" e_name="Sonics"]; Bryan Bowyer, director of ... » read more

Noise At 7nm And Beyond
By Ed Sperling - 14 Dec, 2017 - Comments: 0

The digital and analog worlds always have been very different. Digital engineers see the world in terms of electrons and a well-defined set of numerical values. Their waves are discrete and squared off and their devices are often noisy when they turn on and off. Analog engineers think in terms of quiet, smooth waves, and they are very concerned about anything that can disrupt those waves, such ... » read more

Tech Talk: EM Crosstalk
By Ed Sperling - 14 Dec, 2017 - Comments: 0

Anand Raman, senior director at Helic, talks about the impact of electromagnetic interference on digital design at 10/7nm and beyond. Once confined to the analog space, noise is suddenly an issue at advanced nodes for all designs. At the root of the problem are smaller nodes, increased speed and higher levels of integration. https://youtu.be/hzZqK2lNJNQ » read more

Accounting For Power Earlier
By Ann Mutschler - 14 Dec, 2017 - Comments: 5

Concerns about power usage in an SoC are far from new, but the adoption of power management techniques still varies by company and by project. Leading semiconductor providers have made the necessary changes in tooling and methodology to account for [getkc id="106" kc_name="power awareness"] because they have to, but the rest of the industry hasn't necessarily caught up. “The companies t... » read more

The Return Of Body Biasing
By Ann Mutschler - 15 Nov, 2017 - Comments: 1

Body biasing is making a comeback across a wide swath of process nodes as designers wrestle with how to build mobile devices with more functionality and longer battery life. Consider an ultra-low-power IoT device with a wireless sensor, for example, which is meant to last for years without changing a battery. Body biasing can be used to create an ultra-low-leakage sleep state. “In that ... » read more

Lots Of Little Knobs For Power
By Ann Mutschler - 09 Nov, 2017 - Comments: 3

Dynamic power is becoming a much bigger worry at new nodes as more finFETs are packed on a die and wires shrink to the point where resistance and capacitance become first-order effects. Chipmakers began seeing dynamic power density issues with the first generation of [getkc id="185" kc_name="finFETs"]. While the 3D transistor structures reduced leakage current by providing better gate contro... » read more

Tech Talk: Pseudo SRAM
By Ed Sperling - 26 Oct, 2017 - Comments: 0

eSilicon's Kar Yee Tang explains how to improve performance at 10/7nm without affecting power and area. https://youtu.be/4LI1pBLxxS4 » read more

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