Noise At 7nm And Beyond

Why analog engineers may now get some empathy from the digital side.


The digital and analog worlds always have been very different. Digital engineers see the world in terms of electrons and a well-defined set of numerical values. Their waves are discrete and squared off and their devices are often noisy when they turn on and off. Analog engineers think in terms of quiet, smooth waves, and they are very concerned about anything that can disrupt those waves, such as the noise from digital circuits.

It doesn’t work to just shrink analog circuits like digital logic or memory, which is why when the ITRS roadmap hit 90nm a number of analog companies predicted there would be no more mixed-signal chips. The result turned out to be quite different than they expected at the time. Many of the standard analog IP blocks developed since then have a large portion of digital circuitry within them. While the analog portion doesn’t shrink well, the digital portion was quite amenable to Moore’s Law.

But heading into 7nm and beyond, the analog and digital worlds will come together in a different way. Starting at 7nm, and certainly at 5nm, the dielectric material used to shield small-diameter wires is no longer protecting these circuits effectively. Electrons are being held back by resistance and capacitance effects, which is creating thermal problems that are difficult to track down, let alone stop. In some cases, thin silicon conducts heat well beyond where the problem begins, causing havoc in unexpected places.

These devices are leaking, too. Electrons are tunneling out of these devices, and generating all sorts of unpleasant effects. This is the equivalent of noise in the analog world, only now it’s happening on the digital side. Signal paths, which used to be easy to predict, are being disrupted. Noise from power, stray electrons, heat, magnetism is harder to shield, particularly as distances between various IP blocks continues to shrink with each node. The individual components are smaller, but so are the layers of insulation and the distances between these components.

There is work underway to solve these issues, of course. But like power at 40nm and below, it’s a lot of work to manage. It requires new materials, new processes, and more expensive tools to make sure it all works as planned. All of this makes it harder to verify ahead of time because there are so many possible interactions and corner cases, and much harder to inspect, measure and test.

And now that these advanced-node devices are headed into some mission critical markets, such as automotive AI, it also has to function well enough for 10 or 15 years. Even the definition of what is considered functional is still rather fuzzy. But behind all of this, noise is becoming a much bigger deal. It has now moved squarely in the digital domain. In the past, it was a nuisance. It is now a collection of potentially first-order effects with huge implications for digital as well as mixed-signal designs.

For years, the general consensus was that analog and digital engineers lived in different worlds. To a large extent they still do, but at least now they have something in common to talk about—noise.

Related Stories
Noise Abatement
Will noise compromise your next design? The only way to answer that is to understand which aspects of noise are getting worse and the availability of analysis tools to help mitigate issues.
Tech Talk: Substrate Noise Coupling
How noise can impact the sensitive analog parts of a design, where it comes from, and what to do about it.
Tech Talk: EM Crosstalk
An issue previously confined to analog circuits has become a critical design consideration for digital designs at 10/7nm.
Noise Killed My Chip
Which kind of noise is likely to give your next project a headache, and what you can do about it.
Design For Noise (DfN)
Using direct measurement of noise for better noise-sensitive process control.
Transient Power Problems Rising
At 10/7nm, power management becomes much more difficult; old tricks don’t work.
Transistor Aging Intensifies At 10/7nm And Below
Device degradation becomes limiting factor in IC scaling, and a significant challenge in advanced SoCs.

Leave a Reply

(Note: This name will be displayed publicly)