How noise can impact the sensitive analog parts of a design, where it comes from, and what to do about it.
Roland Jancke, head of the department for design methodology for the Fraunhofer’s Engineering of Adaptive Systems Division, talks with Semiconductor Engineering about the impact of substrate noise coupling on reliability of chips and how to deal with this issue.
Steps are being taken to minimize problems, but they will take years to implement.
AMD CTO Mark Papermaster talks about why heterogeneous architectures will be needed to achieve improvements in PPA.
Companies are speeding ahead to identify the most production-worthy processes for 3D chip stacking.
New capacity planned for 2024, but production will depend on equipment availability.
Number of options is growing, but so is the list of tradeoffs.
Increased transistor density and utilization are creating memory performance issues.
The industry reached an inflection point where analog is getting a fresh look, but digital will not cede ground readily.
Disaggregation and the wind-down of Moore’s Law have changed everything.
FPGAs, CPUs, and equipment receive funding in China; 98 startups raise over $2 billion.
Funding rolls in for photonics and batteries; 88 startups raise $1.3B.
Why UCIe is so important for heterogeneous integration.
Analog foundry expansion; EDA investments; 112 startups raise over $2.6B.
After years of research, chipmakers have started combining ultra low-power designs with advancements in harvesting technology.
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