Customizing Power And Performance

Why balancing these factors is becoming increasingly difficult.


Designing chips is getting more difficult, and not just for the obvious technical reasons. The bigger issue revolves around what these chips going to be used for-and how will they be used, both by the end user and in the context of other electronics.

This was a pretty simple decision when hardware was developed somewhat independently of software, such as in the PC era. Technology generally defined how it could be used rather than the end user. This is still true with smartphones, where systems companies such as Apple, Google and Xiaomi define the most common use cases.

But these rules no longer apply in the worlds of machine learning/deep learning/AI, assisted and autonomous vehicles, virtual and augmented reality, the cloud, or a growing number of vertical slices of the IoT and IIoT. In fact, in most of these new and developing markets, it’s not clear which architectures ultimately will dominate. All of them are in a state of constant evolution.

AI, ML and DL all rely on algorithms that are still being developed and pruned to make them more efficient. And while GPUs seem to have won the training piece, at least for now, it’s not clear what kinds of chips will dominate the inferencing. In the automotive market, Tesla has sparked a race for electrification on the path to autonomous vehicles, but there is no clear or consistent formula for how that will be achieved. It’s even less clear in the AR/VR market, where raw performance is required in a form factor that doesn’t exist yet.

Inside data centers, the compute model is changing, as well. Cloud computing is still trying to figure out the best and most efficient architectures for balancing individual compute tasks that often are unique in terms of data types and volumes, frequency and concentration of processing demands, and inconsistent I/O. And the IoT and IIoT, which frequently are linked to the cloud, are so fragmented that almost everything needs to be custom-built or semi-customized.

The big issue in all of these cases is trying to figure out the right balance between power and performance. How much performance is required at the edge node may be determined by whether there is some intermediate level of computing and what exactly can be handled in the cloud. But that’s not always obvious to the developers of chips that will drive these systems.

That piece of the equation is murky enough. But it gets more complicated by a judgment call about when architectures will be mature enough-if they ever really are-to hardwire everything, or whether some programmability needs to be included into this picture to account for future changes in protocols or the communications fabric or topology. All of these decisions affect performance and power.

Each one of these decisions inevitably leads to the usual problems of noise, signal integrity and thermal effects caused by dynamic power density, current leakage, and RC effects in wires. And that leads to myriad choices involving substrate materials, process nodes and packaging types. But the bigger challenge is figuring out the mix of power and performance from the end user perspective, and that isn’t something chipmakers had to ponder in the past because they were much further removed from the end customer.

The general rule is that power and performance are flip sides of a design. More performance requires more power, and lower power generally equates to lower performance. But in the context of a complex system of multiple chips, systems or subsystems, understanding the power/performance tradeoffs will require a lot more information from throughout the global supply chain than at anytime in the past. And the cost for getting that wrong will be significantly higher.

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