tag: low-power design

TFETs Cut Sub-Threshold Swing
By Katherine Derbyshire - 16 Mar, 2017 - Comments: 0

One of the main obstacles to continued transistor scaling is power consumption. As gate length decreases, the sub-threshold swing (SS) — the gate voltage required to change the drain current by one order of magnitude — increases. As Qin Zhang, Wei Zhao, and Alan Seabaugh of Notre Dame explained in 2006, SS faces a theoretical minimum of 60 mV/decade at room temperature in conventional MO... » read more

The Ultimate Shift Left
By Brian Bailey - 09 Mar, 2017 - Comments: 0

Floorplanning is becoming much more difficult due to a combination of factors—increased complexity of the power delivery network, lengthening of clock trees, rising levels of communication, and greater connectedness of [getkc id="81" kc_name="SoC"]s coupled with highly constrained routing resources. The goal of floorplanning is to determine optimal placement of blocks on a die. But connect... » read more

The Return Of Time Sharing
By Ed Sperling - 16 Feb, 2017 - Comments: 0

As early as the 1960s, it wasn't uncommon to hear that transistors would be free. Those were pretty bold statements at the time, considering most computers in those days cost $1 million, required special rooms, and budding computer scientists usually had to sign up to use mainframe computers for one-hour time slots—often in the middle of the night or on weekends. Still, those predictions ... » read more

Test More Complex For Cars, IoT
By Ann Mutschler - 15 Feb, 2017 - Comments: 0

With increasing focus on safety-critical semiconductors—driven by ADAS, IoT, and security—functional safety concerns are going through the roof. Engineering teams are scrambling to determine how to conduct better in-field or online testing because test no longer can be an afterthought. This has been a common theme across the automotive ecosystem for the past few years, and as the automot... » read more

Fix Processes, Then Silos
By Ed Sperling - 09 Feb, 2017 - Comments: 0

Jack Welch, former CEO of GE, was a big proponent of what he called a "boundaryless corporation." It was a good sound bite, but it pales in comparison to former Intel CEO Andy Grove's philosophy of working out of a cubicle, just like the rest of his staff. While it's great to have corporate buy-in for breaking down silos, which are vertically integrated, the real problem for semiconductor c... » read more

What Can Be Cut From A Design?
By Ann Mutschler - 09 Feb, 2017 - Comments: 0

A long-standing approach of throwing everything into a chip increasingly is being replaced by a focus on what can be left out it. This shift is happening at every level, from the initial design to implementation. After years of trying to fill every square nanometer of real estate on a piece of silicon with memory and logic, doubling the number of [getkc id="26" kc_name="transistors"] from on... » read more

Power State Switching Gets Tougher
By Ann Mutschler - 12 Jan, 2017 - Comments: 0

Power state switching delay is a key factor in minimizing power, and getting it right frequently means the difference between a successful design and a dead chip. But tradeoffs are intricate, complex and often involve judgment calls, making this a place where designs can go completely awry. For years, traditional, full-swing [gettech id="31093" comment="CMOS"] process technologies were used ... » read more

Low-Power Design Is A Corporate Mindset At ARM
By Mentor, a Siemens Business - 07 Dec, 2016 - Comments: 0

The use of the PowerPro platform in the methodology outlined in this paper provides ARM with an RTL design flow which is power-centric. The ability to perform daily RTL power analysis at the block/unit level provides rapid turnaround on the power trend, while weekly analysis provides more complete benchmark reference metrics. To read more, click here. » read more

Timing Closure Issues Resurface
By Ed Sperling - 07 Dec, 2016 - Comments: 1

Timing closure has resurfaced as a major challenge at 10nm and 7nm due to more features and power modes, increased process variation and other manufacturing-related issues. While timing-related problems are roughly correlated to rising complexity in semiconductors, they tend to generate problems in waves—about once per decade. In SoCs, timing closure problems have spawned entire methodolog... » read more

7nm Design Success Starts With Multi-Domain Multi-Physics Analysis
By Arvind Vel - 28 Nov, 2016 - Comments: 1

Companies can benefit from advancements in the latest semiconductor process technology by delivering smaller, faster and lower power products, especially for those servicing mobile, high performance computing and automotive ADAS applications. By using 7nm processes, design teams are able to add a lot more functionality onto a single chip and lower the power consumption by scaling operating volt... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy