Development Tools Enabling The Internet of Things


I'm at the Embedded World conference in Nuremberg this week. Yes, between Mobile World Congress in Barcelona and DVCon in San Jose, Calif., I chose Embedded World. Unfettered by unseasonally late snow and bad weather, it turns out this was the right decision. I have not attended this show for a couple of years and am pleased to find that the show has developed quite a bit. There are more than 8... » read more

Managing Electrical Communications Better


By Ann Steffora Mutschler Managing the electrical components of signal paths between IC, package, board and system is no small task, and it’s only growing in complexity. Understanding how to correctly optimize the communications within a system is critical given that the I/O power is becoming a significant portion of the overall chip power as the number of bits and the speed at which t... » read more

Apple’s Impact On Battery Power


More than one person I’ve spoken with lately has pointed out the fact that battery life is no longer the most important thing when a consumer is choosing a smartphone. Wait! I thought power was the #1, be all end all in the mobile area. It was, until the Apple iPhone showed up on the scene and stole the show, dazzling consumers with the touch screen, unique features, and very Apple-like ex... » read more

Experts At The Table: Obstacles In Low-Power Design


By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss low-power design with with Leah Clark, associate technical director at Broadcom; Richard Trihy, director of design enablement at GlobalFoundries; Venki Venkatesh, engineering director at Atrenta; and Qi Wang, technical marketing group director at Cadence. What follows are excerpts of that conversation. LPHP: What are ... » read more

Transitioning States


By Ann Steffora Mutschler While the concept of finite state machines is mature, understanding their role in design, the transitions between them and how to verify them are fundamental to managing power in today’s large SoCs. In essence, a finite state machine is a set of inputs and outputs and gate bits that describes the operation of the system. “Transitions happen from one state to... » read more

Your Job is Harder Than Mine


What I do for a living is listen – a lot – and try to make sense of the myriad challenges that I hear about in terms of design and managing power and performance. What you do as an architect, design engineer or verification engineer is live in the trenches with it all, every day. I admire and respect that. This is especially true as I recently pondered and talked with industry luminaries... » read more

Power Mode And State


By Luke Lang Low-power designs that use power shutoff (PSO) and multiple-supply voltage (MSV) will have circuits that operate at various voltages, including no voltage. To describe the combination of allowable voltages in a design, CPF uses power mode, and UPF 1.0 uses power state. In CPF, each power mode represents one combination of the states of all power domains. In UPF 1.0, each power ... » read more

Leveraging The Past


By Ann Steffora Mutschler It’s easy to forget that not every design today is targeted at 20nm, given the amount of focus put on the bleeding edge of technology. But in fact a large number of designs utilize the stability and reliability of older manufacturing nodes, as well as lower mask costs, by incorporating new design and verification techniques, with 2.5D designs being a prime example. ... » read more

Training The Next Gen For Low Power


Reflecting on my time at this year's Design Automation Conference, I am quickly reminded that I work in the most fascinating industry I can think of. Having the opportunity to discuss deep technical low power design issues, forward-looking challenges as well as the business implications face to face with thought leaders is inspiring and invigorating. With the amount of brain power filling Mosco... » read more

Traversing The Abstraction Landscape


By Ann Steffora Mutschler Back in the early days of semiconductor design engineers could count the number of transistors on their chip with their own two eyes. They designed and worked at the same level of design abstraction when doing the timing analysis. Tools were SPICE-like, maybe abstracted with slightly simpler timing models than the SPICE-level transistor models. Thanks to Moore’... » read more

← Older posts Newer posts →