tag: low-power design

Why Comparing Processors Is So Difficult
By Brian Bailey - 10 Mar, 2022 - Comments: 2

Every new processor claims to be the fastest, the cheapest, or the most power frugal, but how those claims are measured and the supporting information can range from very useful to irrelevant. The chip industry is struggling far more than in the past to provide informative metrics. Twenty years ago, it was relatively easy to measure processor performance. It was a combination of the rate at ... » read more

Why Data Center Power Will Never Come Down
By Bryon Moyer - 10 Feb, 2022 - Comments: 3

Data centers have become significant consumers of energy. In order to deal with the proliferation of data centers and the servers within them, there is a big push to reduce the energy consumption of all data center components. With all that effort, will data center power really come down? The answer is no, despite huge improvements in energy efficiency. “Keeping data center power consum... » read more

SoC Power Methodology: Are We Lean Enough
By Siemens EDA - 09 Feb, 2022 - Comments: 0

It’s interesting how past lessons learned have such relevance in today’s quest for an optimum system-on chip (SoC) power methodology. Lean manufacturing was introduced by the Toyota Motor Corporation in the 1930s. It is now an essential methodology in most manufacturing and industrial settings. As lean methodology evolved, it extended to software development where its principles have led to... » read more

Always-On DSPs
By Ed Sperling - 28 Dec, 2021 - Comments: 0

There are tradeoffs between powering circuits down to save power and waking them up to respond to voice and visual commands. Prakash Madhvapathy, director of product marketing and product management at Cadence, talks about the best ways to deploy digital signal processors, why multiple DSPs are often better than just one, and what penalties there are for various approaches. » read more

Batteries Take Center Stage
By Heidi Elliott - 27 Dec, 2021 - Comments: 0

For any mobile electronic device, the biggest limiting factors are the size, age, type, and utilization of the batteries. Battery technology is improving on multiple fronts. The batteries themselves are becoming more efficient. They are storing more energy per unit of area, and work is underway to provide faster charging and to increase the percentage of that energy that can be used, as well... » read more

Can Coherent Optics Reduce Data-Center Power?
By Bryon Moyer - 09 Dec, 2021 - Comments: 0

As optical bandwidth requirements increase, system designers are turning to “coherent” modulation schemes that can place more data on the same laser light, and lower power over long connections. A newer question is whether those savings could be achieved for short connections within data centers, as well. “Coherent is the direction everything's moving, because for a given system and... » read more

Aprisa Place-And-Route For Low-Power SoCs
By Siemens EDA - 10 Nov, 2021 - Comments: 0

The Aprisa digital design software helps designers address the many challenges of low-power designs. Aprisa is the most flexible IC place-and-route tool on the market—it accepts all industry-standard power formats, has excellent correlation to third-party signoff tools, and is easy to install, set up, and use. With effective technology and impressive usability, the Aprisa software ensures cos... » read more

Get Ready For The Next Generation Of Wearable Tech
By Brian Bailey - 18 Oct, 2021 - Comments: 0

Wearables have attracted a lot of attention recently, due to both their successes as well as failures. They bring together requirements for packaging, new substrates, power scavenging, low-power, novel connectivity, flexibility, durability, as well as fashion. While some of the challenges remain formidable, the long-term potential is driving the industry to look at what is possible. They are... » read more

Power-Aware Test: Addressing Power Challenges In DFT And Test
By Rahul Singhal - 10 Aug, 2021 - Comments: 0

Integrated circuit (IC) sizes continue to grow as they meet the compute requirements of cutting-edge applications such as artificial intelligence (AI), autonomous driving, and data centers. As design sizes increase, the total power consumption of the chip also increases. While process node scaling reduces a transistor’s size and its operating-voltage, power scaling has not kept up with the si... » read more

Lower Power Chips: What To Watch Out For
By Ann Mutschler - 08 Jul, 2021 - Comments: 0

Low-power design in advanced nodes and advanced packaging is becoming a multi-faceted, multi-disciplinary challenge, where a long list of issues need to be solved both individually and in the context of other issues. With each new leading-edge process node, and with increasingly dense packaging, the potential for problematic interactions is growing. That, in turn, can lead to poor yield, cos... » read more

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