tag: low-power design

Always-On DSPs
By Ed Sperling - 28 Dec, 2021 - Comments: 0

There are tradeoffs between powering circuits down to save power and waking them up to respond to voice and visual commands. Prakash Madhvapathy, director of product marketing and product management at Cadence, talks about the best ways to deploy digital signal processors, why multiple DSPs are often better than just one, and what penalties there are for various approaches. » read more

Batteries Take Center Stage
By Heidi Elliott - 27 Dec, 2021 - Comments: 0

For any mobile electronic device, the biggest limiting factors are the size, age, type, and utilization of the batteries. Battery technology is improving on multiple fronts. The batteries themselves are becoming more efficient. They are storing more energy per unit of area, and work is underway to provide faster charging and to increase the percentage of that energy that can be used, as well... » read more

Can Coherent Optics Reduce Data-Center Power?
By Bryon Moyer - 09 Dec, 2021 - Comments: 0

As optical bandwidth requirements increase, system designers are turning to “coherent” modulation schemes that can place more data on the same laser light, and lower power over long connections. A newer question is whether those savings could be achieved for short connections within data centers, as well. “Coherent is the direction everything's moving, because for a given system and... » read more

Aprisa Place-And-Route For Low-Power SoCs
By Siemens EDA - 10 Nov, 2021 - Comments: 0

The Aprisa digital design software helps designers address the many challenges of low-power designs. Aprisa is the most flexible IC place-and-route tool on the market—it accepts all industry-standard power formats, has excellent correlation to third-party signoff tools, and is easy to install, set up, and use. With effective technology and impressive usability, the Aprisa software ensures cos... » read more

Get Ready For The Next Generation Of Wearable Tech
By Brian Bailey - 18 Oct, 2021 - Comments: 0

Wearables have attracted a lot of attention recently, due to both their successes as well as failures. They bring together requirements for packaging, new substrates, power scavenging, low-power, novel connectivity, flexibility, durability, as well as fashion. While some of the challenges remain formidable, the long-term potential is driving the industry to look at what is possible. They are... » read more

Power-Aware Test: Addressing Power Challenges In DFT And Test
By Rahul Singhal - 10 Aug, 2021 - Comments: 0

Integrated circuit (IC) sizes continue to grow as they meet the compute requirements of cutting-edge applications such as artificial intelligence (AI), autonomous driving, and data centers. As design sizes increase, the total power consumption of the chip also increases. While process node scaling reduces a transistor’s size and its operating-voltage, power scaling has not kept up with the si... » read more

Lower Power Chips: What To Watch Out For
By Ann Mutschler - 08 Jul, 2021 - Comments: 0

Low-power design in advanced nodes and advanced packaging is becoming a multi-faceted, multi-disciplinary challenge, where a long list of issues need to be solved both individually and in the context of other issues. With each new leading-edge process node, and with increasingly dense packaging, the potential for problematic interactions is growing. That, in turn, can lead to poor yield, cos... » read more

Shifting Toward Data-Driven Chip Architectures
By Ed Sperling and Ann Mutschler - 16 Jun, 2021 - Comments: 0

An explosion in data is forcing chipmakers to rethink where to process data, which are the best types of processors and memories for different types of data, and how to structure, partition and prioritize the movement of raw and processed data. New chips from systems companies such as Google, Facebook, Alibaba, and IBM all incorporate this approach. So do those developed by vendors like Appl... » read more

Power Optimization: What’s Next?
By Brian Bailey - 17 May, 2021 - Comments: 2

Concerns about the power consumed by semiconductors has been on the rise for the past couple of decades, but what can we expect to see coming in terms of analysis and automation from EDA companies, and is the industry ready to make the investment? Ever since Dennard scaling stopped providing automatic power gains by going to a smaller geometry, circa 2006, semiconductors have been increasing... » read more

11 Ways To Reduce AI Energy Consumption
By Bryon Moyer - 13 May, 2021 - Comments: 1

As the machine-learning industry evolves, the focus has expanded from merely solving the problem to solving the problem better. “Better” often has meant accuracy or speed, but as data-center energy budgets explode and machine learning moves to the edge, energy consumption has taken its place alongside accuracy and speed as a critical issue. There are a number of approaches to neural netw... » read more

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