tag: low-power verification

What’s Missing In Low-Power Verification
By Ed Sperling - 09 May, 2013 - Comments: 0

By Ed Sperling Ask two engineers what low-power verification is and you’ll likely get the same checklist that includes confidence in the overall design, good coverage, a long list of corner cases, and other items in a checklist. Ask them how to reach that goal you’ll almost certainly get different answers—or maybe no answers at all. Power has emerged as a ubiquitous concern in design,... » read more

Power-Up Low-Power Verification
By Adam Sherer - 09 May, 2013 - Comments: 0

By Adam Sherer When facing low-power verification in the SoC world, everyone could use a few power-ups just like Nintendo’s little plumber, Mario. Sure, Mario could run and jump through a lot of terrain, but when he hit some new challenges he could rely on some new tools and techniques to get him through. Completing your first SoC with a single power control module (PCM) and domain is lik... » read more

The Power Problem
By Ed Sperling - 09 May, 2013 - Comments: 0

For the past few years, EDA companies have been warning chipmakers that power will become the biggest issue they face at future nodes. They were right. While it may not be the only big problem—after all, the number of issues at each new tick of Moore’s Law is growing—power is certainly one of the most challenging and by far the most pervasive. In fact, the warnings about just how perni... » read more

Experts At The Table: The Trouble With Low-Power Verification
By Ed Sperling - 29 Mar, 2013 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss low-power verification with Leah Clark, associate technical director at Broadcom; Erich Marschner, product marketing manager at Mentor Graphics; Cary Chin, director of marketing for low-power solutions at Synopsys; and Venki Venkatesh, senior director of engineering at Atrenta. What follows are excerpts of that conversat... » read more

Best Practices
By Tom Fitzpatrick - 14 Mar, 2013 - Comments: 0

By Tom Fitzpatrick Active power control management for low-power designs has become a hot topic, especially with the latest update to the Unified Power Format standard. Version 2.1 was approved by IEEE on March 6, 2013. UPF gives the ability to specify power control for different parts of a design, separate from the RTL itself. The advent of low-power design has greatly increased the comple... » read more

Experts At The Table: The Trouble With Low-Power Verification
By Ed Sperling - 14 Mar, 2013 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss low-power verification with Leah Clark, associate technical director at Broadcom; Erich Marschner, product marketing manager at Mentor Graphics; Cary Chin, director of marketing for low-power solutions at Synopsys; and Venki Venkatesh, senior director of engineering at Atrenta. What follows are excerpts of that conversat... » read more

LP Verification
By Ed Sperling - 08 Mar, 2013 - Comments: 0

Functional verification has been a consideration throughout the design flow for the past several process nodes. Low power verification has been more of an afterthought. That’s beginning to change, though, as the challenge of integrating IP blocks and the physical effects of shrinking wires and RC delays in interconnects begin affecting power and performance in designs. What’s becoming cl... » read more

Unified Power Intent
By Ed Sperling - 01 Mar, 2013 - Comments: 0

The next version of the Unified Power Format has been approved, bridging the major differences between UPF/IEEE 1801 and the Common Power Format. For anyone who works in low-power verification, this is very good news. The new standard is the result of an unprecedented collaboration by chipmakers and EDA companies, and the people who devised a solution to this problem deserve a big pat on the... » read more

The New Frontier: Low-Power Verification And Test
By Ed Sperling - 09 Aug, 2012 - Comments: 0

By Ann Steffora Mutschler By now there’s no argument that verification and test strategies must be considered at the very earliest stages of any design cycle, and when it comes to low-power designs, the advanced techniques used and design complexity make the challenges here even more daunting. Low-power verification and test strategies have been in development for a number of years, and it... » read more

The Trouble With Low-Power Verification
By Ed Sperling - 04 Nov, 2010 - Comments: 0

By Ed Sperling If verification accounts for 70% of the non-recurring engineering expenses in a design, what percentage does verifying a low-power design actually consume? Answer: No one knows for sure. The reason has more to do with insufficient data than tools, processes or flows. That’s also the reason that power models have never been created for more than a single design. “Power... » read more

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