tag: MAC

New Age Solution For Data Integrity And Authenticity
By Om Prakash - 27 Jun, 2023 - Comments: 0

With the advent of faster processing chips, the rate of data transfer has increased enormously. Be it artificial intelligence (AI), the Internet of Things (IOT), compute intensive analytics, or cloud computing, the demand for processing data in a fraction of a second is huge. Chips with superfast computing capabilities are used in applications where malfunctions can be life threatening, such as... » read more

MAC Operation on 28nm High-k Metal Gate FeFET-based Memory Array with ADC (Fraunhofer IPMS/GF)
By Technical Paper Link - 01 Dec, 2022 - Comments: 0

A technical paper titled "Demonstration of Multiply-Accumulate Operation With 28 nm FeFET Crossbar Array" was published by researchers at Fraunhofer IPMS and GlobalFoundries. Abstract "This letter reports a linear multiply-accumulate (MAC) operation conducted on a crossbar memory array based on 28nm high-k metal gate (HKMG) Complementary Metal Oxide Semiconductor (CMOS) and ferroelectric fi... » read more

NeuroSim Simulator for Compute-in-Memory Hardware Accelerator: Validation and Benchmark
By Technical Paper Link - 20 Dec, 2021 - Comments: 0

Abstract:   "Compute-in-memory (CIM) is an attractive solution to process the extensive workloads of multiply-and-accumulate (MAC) operations in deep neural network (DNN) hardware accelerators. A simulator with options of various mainstream and emerging memory technologies, architectures, and networks can be a great convenience for fast early-stage design space exploration of CIM hardw... » read more

Von Neumann Is Struggling
By Brian Bailey - 18 Jan, 2021 - Comments: 5

In an era dominated by machine learning, the von Neumann architecture is struggling to stay relevant. The world has changed from being control-centric to one that is data-centric, pushing processor architectures to evolve. Venture money is flooding into domain-specific architectures (DSA), but traditional processors also are evolving. For many markets, they continue to provide an effective s... » read more

More Multiply-Accumulate Operations Everywhere
By Ed Sperling - 02 Apr, 2020 - Comments: 1

Geoff Tate, CEO of Flex Logix, sat down with Semiconductor Engineering to talk about how to build programmable edge inferencing chips, embedded FPGAs, where the markets are developing for both, and how the picture will change over the next few years. SE: What do you have to think about when you're designing a programmable inferencing chip? Tate: With a traditional FPGA architecture you ha... » read more

Tradeoffs In Embedded Vision SoCs
By Ed Sperling - 28 Jan, 2020 - Comments: 0

Gordon Cooper, product marketing manager for embedded vision processors at Synopsys, talks with Semiconductor Engineering about the need for more performance in these devices, how that impacts power, and what can be done to optimize both prior to manufacturing. » read more

Memory Subsystems In Edge Inferencing Chips
By Ed Sperling - 23 Sep, 2019 - Comments: 0

Geoff Tate, CEO of Flex Logix, talks about key issues in a memory subsystem in an inferencing chip, how factors like heat can affect performance, and where these kinds of chips will be used. » read more

eFPGA Macros Deliver Higher Speeds from Less Area/Resources
By Geoff Tate - 05 Sep, 2019 - Comments: 0

We work with a lot of customers designing eFPGA into their SoCs.  Most of them have “random logic” RTL, but some customers have large numbers of complex, frequently used blocks. We have found in many cases that we can help the customer achieve higher throughput AND use less silicon area with Soft Macros. Let’s look at an example: 64x64 Multiply-Accumulate (MAC), below: If yo... » read more

How To Improve ML Power/Performance
By Ed Sperling - 12 Jul, 2019 - Comments: 0

Raymond Nijssen, vice president and chief technologist at Achronix, talks about the shift from brute-force performance to more power efficiency in machine learning processing, the new focus on enough memory bandwidth to keep MAC functions busy, and how dynamic range, precision and locality can be modified to improve speed and reduce power. » read more

Week in Review: IoT, Security, Auto
By Jeff Dorsch - 12 Jul, 2019 - Comments: 0

Products/Services Arteris IP reports that Bitmain licensed the Arteris Ncore Cache Coherent Interconnect intellectual property for use in its next-generation Sophon Tensor Processing Unit system-on-a-chip devices for the scalable hardware acceleration of artificial intelligence and machine learning algorithms. “Our choice of interconnect IP became more important as we continued to increase t... » read more

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