The Race To Zero Defects


By Jeff Dorsch and Ed Sperling Testing chips is becoming more difficult, more time-consuming, and much more critical—particularly as these chips end up in cars, industrial automation, and a variety of edge devices. Now the question is how to provide enough test coverage to ensure that chips will work as expected without slowing down the manufacturing process or driving up costs. Balanci... » read more

Democratized Autonomous Vehicle System Design


The major question facing automotive equipment vendors and OEMs working to bring autonomous vehicles to market: how to address the additional cost and power of these new electronic systems while reducing system latency and improving manufacturability? TIRIAS Research says the DRS360 Autonomous Driving Platform provides an answer. To read more, click here. » read more

Using Automated Pattern Matching For SRAM Physical Verification


How often have you struggled to verify static random-access memory (SRAM) blocks in your design? And how often, no matter how much time you spend on them, do they end up causing manufacturing issues? Memory is a critical component in today’s SoC designs, often consuming 50% or more of the die area. SRAM blocks are typically assembled in a layout using a set of specific intellectual propert... » read more

Paving The Way To 16/14nm


The move to the next stop on the Moore’s Law road map isn’t getting any less expensive or easier, but it is becoming more predictable. Tools and programs are being expanded to address physical effects such as electrostatic discharge (ESD), electromigration and thermal effects from increased current density. Any or all of these three checklist items can affect the reliability of a chip. A... » read more