SRAM In AI: The Future Of Memory


Experts at the Table: Semiconductor Engineering sat down to talk about AI and the latest issues in SRAM with Tony Chan Carusone, CTO at Alphawave Semi; Steve Roddy, chief marketing officer at Quadric; and Jongsin Yun, memory technologist at Siemens EDA. What follows are excerpts of that conversation. SE: What are the key characteristics of SRAM that will make it suitable for AI workloads... » read more

Power/Performance Bits: May 6


Compressing objects Computer scientists at MIT propose a way to improve data compression in memory by focusing on objects rather than cache lines. "The motivation was trying to come up with a new memory hierarchy that could do object-based compression, instead of cache-line compression, because that's how most modern programming languages manage data," said Po-An Tsai, a graduate student at... » read more

Tech Talk: Data-Driven Design


Steven Woo, distinguished inventor at Rambus, talks about memory hierarchies and how they are changing as the amount of data continues to grow. https://youtu.be/4FwZ1YeQa18 » read more

New Memory Approaches And Issues


New memory types and approaches are being developed and tested as DRAM and Moore's Law both run out of steam, adding greatly to the confusion of what comes next and how that will affect chip designs. What fits where in the memory hierarchy is becoming less clear as the semiconductor industry grapples with these changes. New architectures, such as [getkc id="202" kc_name="fan-outs"] and [getk... » read more

Architecturally Optimizing Memory Bandwidth


Making sure that an SoC’s [getkc id="22" kc_name="memory"] bandwidth is optimized is a crucial part of the design process today given its significance toward overall system performance. There are many ways to approach this issue, and all of them can have a direct bearing on the competitiveness of a chip in terms of both power and performance. So where should you start? “Number one, c... » read more