tag: memory

Improving Performance And Simplifying Coding With XY Memory’s Implicit Parallelism
By Synopsys - 08 Mar, 2022 - Comments: 0

Instruction-level Parallelism (ILP) refers to design techniques that enable more than one RISC instruction to be executed simultaneously in the same instruction, which boosts processor performance by increasing the amount of work done in a given time interval, thereby increasing the throughput. This parallelism can be explicit, where each additional instruction is explicitly part of the instruc... » read more

2022 Chip Forecast: Mixed Signals
By Mark LaPedus - 22 Feb, 2022 - Comments: 0

Jim Feldhan, president of Semico Research, sat down with Semiconductor Engineering to talk about the outlook for the semiconductor market. SE: What was your final 2021 semiconductor forecast? What is your 2022 semiconductor forecast? Feldhan: For 2021, world semiconductor revenues totaled $558 billion and units totaled over 1.1 trillion units. In terms of growth rate, revenues increased 2... » read more

It’s Official: HBM3 Dons The Crown Of Bandwidth King
By Frank Ferro - 10 Feb, 2022 - Comments: 0

With the publishing of the HBM3 update to the High Bandwidth Memory (HBM) standard, a new king of bandwidth is crowned. The torrid performance demands of advanced workloads, with AI/ML training leading the pack, drive the need for ever faster delivery of bits. Memory bandwidth is a critical enabler of computing performance, thus the need for the accelerated evolution of the standard with HBM3 r... » read more

Thin Quad Die Package (QDP) Development
By Shaun Bowers - 20 Jan, 2022 - Comments: 0

In the world of solid-state memory fabs, bits per mm2 rule. In the memory packaging market, mm2 of silicon per a given package thickness is the defining feature. Both the memory architecture of the wafer and the package technology take advantage of 3D structures to achieve best in class bit density. In the case of the wafer fab, 3D NAND and other technologies are pushing the envelope to meet ev... » read more

HyperRAM As A Low Pin-Count Expansion Memory For Embedded Systems
By Infineon - 12 Jan, 2022 - Comments: 0

Rapid advances in microelectronics are driving mega trends across industries, creating a need for new technologies and optimized devices with better performance. With large volumes of data being made available due to the increasing content of electronics in automotive, industrial, smart home and IoT devices, there is a requirement to seamlessly process and render information. Application platfo... » read more

Scaling DDR5 RDIMMs To 5600 MT/s
By John Eble - 09 Dec, 2021 - Comments: 0

Looking forward to 2022, the first of the DDR5-based servers will hit the market with RDIMMs running at 4800 megatransfers per second (MT/s). This is a 50% increase in data rate over top-end 3200 MT/s DDR4 RDIMMs in current high-performance servers. DDR5 memory incorporates a number of innovations, such as Decision Feedback Equalization (DFE), and a new DIMM architecture which enable that speed... » read more

Outlook: DRAM, NAND, Next-Gen Memory
By Mark LaPedus - 18 Nov, 2021 - Comments: 0

Jim Handy, director at Objective Analysis, sat down with Semiconductor Engineering to talk about the 3D NAND, DRAM and next-generation memory markets. What follows are excerpts of that discussion. SE: How would you characterize the NAND market thus far in 2021? Handy: All chips are seeing unusual strength in 2021, but NAND flash and DRAM are doing what they usually do by exhibiting more e... » read more

A Deeper Look into RowHammer’s Sensitivities: Experimental Analysis of Real DRAM Chips and Implications on Future Attacks and Defenses
By Technical Paper Link - 14 Nov, 2021 - Comments: 0

Abstract "RowHammer is a circuit-level DRAM vulnerability where repeatedly accessing (i.e., hammering) a DRAM row can cause bit flips in physically nearby rows. The RowHammer vulnerability worsens as DRAM cell size and cell-to-cell spacing shrink. Recent studies demonstrate that modern DRAM chips, including chips previously marketed as RowHammer-safe, are even more vulnerable to RowHammer than... » read more

HBM2E Raises The Bar For Memory Bandwidth
By Rambus - 10 Nov, 2021 - Comments: 0

AI/ML training capabilities are growing at a rate of 10X per year driving rapid improvements in every aspect of computing hardware and software. HBM2E memory is the ideal solution for the high bandwidth requirements of AI/ML training, but entails additional design considerations given its 2.5D architecture. Designers can realize the full benefits of HBM2E memory with the silicon-proven memory s... » read more

More Errors, More Correction in Memories
By Bryon Moyer - 09 Nov, 2021 - Comments: 1

As memory bit cells of any type become smaller, bit error rates increase due to lower margins and process variation. This can be dealt with using error correction to account for and correct bit errors, but as more sophisticated error-correction codes (ECC) are used, it requires more silicon area, which in turn drives up the cost. Given this trend, the looming question is whether the cost of ... » read more

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