tag: Mentor Graphics

Blog Review: July 2
By Ed Sperling - 02 Jul, 2014 - Comments: 0

Mentor’s Nazita Saye has reservations about driverless cars. Sometimes it’s actually fun to drive—and sometimes it isn’t. Cadence’s Brian Fuller is a bit more optimistic about driverless cars. He says that from the standpoint of safety, efficiency and environment, autonomous vehicles will be a big step forward—if and when some critical problems are solved. And along the same... » read more

The Week In Review: Design
By Ed Sperling - 27 Jun, 2014 - Comments: 0

Tools eSilicon uncorked a GDSII online quote system for TSMC, which allows chipmakers to pick a variety of information ranging from process technology to package to yield and tapeout and production forecast and get a quote within minutes. This is a new twist in the value chain provider market. Synopsys added program to speed up FPGA-based prototype creation, which includes approved third-pa... » read more

Moore’s Law Tail No Longer Wagging The Dog
By Brian Bailey - 26 Jun, 2014 - Comments: 3

In a recent special report titled “Will 7nm and 5nm really happen?” Semiconductor Engineering outlined the progress being made for new production nodes and the progress being made to overcome the technological challenges that they contain. But who are the likely candidates for those new nodes and who is going to pay for their development, including the EDA tools that will be necessary to ut... » read more

Can EDA Keep Growing?
By Ed Sperling - 26 Jun, 2014 - Comments: 0

Slower progress at the leading edge of process technology, coupled with rising costs and fewer design starts, are changing the economics of the EDA world. Not surprisingly, there is almost a direct correlation between the shrinking number of startups in the field and the number of customers working on the most advanced nodes. So what exactly does this mean for the EDA world? Big changes, for... » read more

Semiconductor R&D Crisis Ahead?
By Ed Sperling - 26 Jun, 2014 - Comments: 0

Listen to engineering management at chipmakers these days and a consistent theme emerges: They’re all petrified about where to place their next technology bets. Do they move to 14/16nm finFETs with plans to shrink to 10nm, 7nm and maybe even 5nm? Do they invest in 2.5D and 3D stacked die? Or do they eke more from existing process nodes using new process technologies, more compact designs and ... » read more

Which Group Should Create System Models?
By Jon McDonald - 26 Jun, 2014 - Comments: 0

One of the factors affecting adoption of a system-level flow is identifying who will do the work to create the system model. For most organizations it's not something they have allocated to a specific group. Generally when an ESL flow is deployed, the software developers, architects and hardware designers will all benefit from the investment, so it would be reasonable that they all contribut... » read more

Without Moore’s Law: EDA
By Brian Bailey - 26 Jun, 2014 - Comments: 3

Semiconductor Engineering is examining the assertion about the end of Moore’s Law in a number of different ways. The special report, “Will 7nm and 5nm really happen?” looked at the technical aspects related to continuing into finer geometries. “Moore’s Law Tail No Longer Wagging the Dog” asked the question about the economics of people being able to afford to go to the latest node. ... » read more

Efficient Noise Analysis For Complex Non-Periodic Analog/RF Blocks
By Mentor, a Siemens Business - 25 Jun, 2014 - Comments: 0

Noise minimization is a required design objective for advanced analog and RF circuits. Unlike digital circuits, where noise is a second-order effect, noise in analog and RF circuits directly affects system performance metrics such as signal to noise ratio (SNR) and bit error rate (BER). Effective design optimization in the presence of random device noise is challenging because the noise sources... » read more

Blog Review: June 25
By Ed Sperling - 25 Jun, 2014 - Comments: 0

Is the Amazon Fire smart phone a paradigm shift? Cadence’s Brian Fuller looks at the first application-specific smart phone and why it’s noteworthy—regardless of how well it fares against phones made by Apple and Samsung. Rambus’ Deepak Chandra Sekar digs deep into interconnect technology and where the prevailing winds are blowing—copper barrier/cap/liner optimization, a slowdown i... » read more

Tech Talk: Photonics, Take 2
By Ed Sperling - 23 Jun, 2014 - Comments: 0

Mentor Graphics’ John Ferguson explains why light is getting so much attention for inter-chip communications, where it excels, and why it has limitations. This is the second part in a two-part series. [youtube vid=4-5FbxIpIk4] To view part 1, click here. » read more

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