tag: Mentor Graphics

Improving Design Reliability By Avoiding Electrical Overstress
By Various Writers - 21 Nov, 2013 - Comments: 0

Electrical overstress (EOS) is one of the leading causes of IC failures across all semiconductor manufacturers, and is responsible for the vast majority of device failures and product returns. The use of multiple voltages increases the risk of EOS, so IC designers need to increase their diligence to ensure that thin-oxide digital transistors do not have direct or indirect paths to high-voltage ... » read more

Rethinking Old Sayings
By Jon McDonald - 21 Nov, 2013 - Comments: 0

One of my favorite quotes from Gary Smith is a few years old: “It’s the software, stupid!” That statement was made way back in 2006. While it was, and in some ways still is, very illustrative, I believe it also points to one extreme in the back and forth between focusing on hardware then software to differentiate our electronic systems. At the point in time Gary made the statement that... » read more

Stacked Die Moves From Drawing Board To Reality
By Ed Sperling - 21 Nov, 2013 - Comments: 0

After decades of moving in a straight line from one process geometry shrink to the next, much of the semiconductor industry has taken a step back to figure out what comes next. While companies such as Intel, IBM and Samsung continue to look as far ahead as the 3nm process node, along with new materials to improve electron mobility and new transistor designs based on electron tunneling and carbo... » read more

Blog Review: Nov. 20
By Ed Sperling - 20 Nov, 2013 - Comments: 0

Can you really heat your home office with just four candles? It all depends on where you put those candles, as Mentor’s Robin Bornoff shows in part one of this series. And make sure you check out the video, particularly if you’ve had a tough day. Synopsys’ Karen Bartleson interviews ST’s Oleg Logvinov on camera about the IoT, which may be the biggest change since the Industrial Revol... » read more

IP Ecosystem Solutions For Complex Systems
By Joanne Itow - 14 Nov, 2013 - Comments: 0

At the Semico Impact Conference: Focus on the IP Ecosystem, Mahesh Tirupattur, Executive Vice President, Analog Bits, challenged four panelists to an engaging discussion on their approach to IP Ecosystem Solutions for Complex Systems. Panel participants included Dan Kochpatcharin, Deputy Director, IP Portfolio Management, TSMC; Jason Polychronopoulos, Mentor Graphics; Chris Rowen, Cadence Fello... » read more

From DFM To IFM
By Ed Sperling - 14 Nov, 2013 - Comments: 0

For the past decade the bridge between design and manufacturing was called, appropriately enough, design for manufacturing. DFM tools, which by nature cross boundaries of what previously were discrete segments in the semiconductor flow, are now critical for complex designs. They allow design teams to check early in the design process whether chips will yield sufficiently and to incorporate rule... » read more

The Trouble With Triples—Part 1
By David Abercrombie - 14 Nov, 2013 - Comments: 0

If you’re a true geek like me, you may remember the Star Trek episode “The Trouble with Tribbles,” about the cute furry little aliens that purr when you pet them. They seemed so nice and friendly on the surface, but in the end, they became an exponentially growing mass of ravenous monsters that almost broke down the ship and consumed the storehouse of grain that was meant to provide human... » read more

Improve Logic Test With A Hybrid ATPG/BIST Solution
By Various Writers - 14 Nov, 2013 - Comments: 0

Two test strategies are used to test virtually all IC logic—automatic test pattern generation (ATPG) with test pattern compression, and logic built-in self-test (BIST). For many years, there was a passionate debate between some DFT practitioners about which is the best test method— ATPG or BIST. ATPG has been dominant for years, and is now used for full-chip test across the electronics indu... » read more

Blog Review: Nov. 13
By Ed Sperling - 13 Nov, 2013 - Comments: 0

Synopsys’ Brent Gregory digs into optimal paths—in this case between the bakery, the library and another store. This is the classic traveling salesman equation, but with a large sales staff and lots of stops. Mentor’s Michael Ford points to the gap between supply-chain and shop-floor management solutions. This is yet another example of thinking outside the package—and maybe the enti... » read more

Executive Viewpoint: Atoptech’s Jue-Hsien Chern
By Brian Bailey - 13 Nov, 2013 - Comments: 0

What is the difference between skyscrapers and chips? Dr Chern has worked on both and he says it’s all about how you apply margins. Jue-Hsien Chern started his technology career earning a M.S. and B.S. in Engineering from National Taiwan University and majored in structural engineering — bridges, dams, tunnels and high-rise buildings, all of which had to withstand earthquakes. That is a ... » read more

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