tag: Mentor Graphics

Too Big To Handle?
By Ann Mutschler - 08 Aug, 2013 - Comments: 0

By Ann Steffora Mutschler With the insatiable demand for power efficiency today, the power management tasks have been pushed up into the realm of the software engineer due to the sheer complexity of the hardware design and the demands on the hardware designer to get their part right. Managing power properly in embedded software boils down to really understanding the application and how it i... » read more

How Secure Is Your SoC?
By Ed Sperling - 07 Aug, 2013 - Comments: 0

The Russian Federal Guard Service’s decision to revert to typewriters—machines that leave unique mechanical fingerprints—is a good indicator of just how serious security has become in a world dominated by electronics and pervasive connectivity. What’s less apparent is the growing threat at the SoC level—inside complex chips, between the chip and the board, and between chips on the ... » read more

Next Phase Of Energy Efficiency Begins
By Ed Sperling - 02 Aug, 2013 - Comments: 0

Individual purchases and product rollouts by companies are difficult to assess by themselves. Sometimes they are isolated steps that have no context or connection to anything else—the proverbial toe-dipping exercise to see just how deep and cold the water is. Other times, they are the beginning of a huge market shift. In the mobile space—and increasingly in everything that mobile devices... » read more

Experts At The Table: Automotive Electronics
By Ann Mutschler - 02 Aug, 2013 - Comments: 0

By Ann Steffora Mutschler System-Level Design sat down to discuss the opportunities in automotive electronics with Alexandre Palus, principal SoC architect at Altera; Aveek Sarkar, VP of product engineering & support at Apache; Mladen Nizic, engineering director, mixed signal solution at Cadence; and Stephen Pateras, product marketing director, silicon test solutions at Mentor Graphics. W... » read more

Blog Review: July 31
By Ed Sperling - 31 Jul, 2013 - Comments: 0

By Ed Sperling Wherever you turn in IC design, there’s always someone talking about future problems involving the interconnect. Cadence’s Brian Fuller puts the latest speech by North Carolina State professor Paul Franzon in historical perspective—or at least in the shadow of the last dire prediction by Intel’s Mark Bohr two decades ago. Incidentally, Bohr’s warning turned out to be r... » read more

Garbage Or Treasure?
By Jon McDonald - 27 Jul, 2013 - Comments: 0

By Jon McDonald “Garbage in, garbage out” is a very appropriate axiom to keep in mind as you consider what kind of system-level modeling to invest in. Unfortunately this can be complicated by considering another piece of wisdom that often applies as well: “One mans trash is another’s treasure.” What might be an inappropriate abstraction for one type of analysis may be very accepta... » read more

FPGA Verification with Assertions: Why Bother?
By Various Writers - 27 Jul, 2013 - Comments: 0

This paper provides a practical, easy, step-by- step set of instructions on how to add assertions to your RTL design. By following the simple guidelines provided in this paper you will benefit by cutting simulation debugging time in half, as well as finding very complex bugs that are likely to escape traditional simulation without assertions. To download this white paper, click here. » read more

EM Analysis At Advanced Nodes
By Valeriy Sukharev - 26 Jul, 2013 - Comments: 0

Going forward, a very different method of EM assessment can be proposed if we look at interconnect reliability from the position of its functionality, when the failure of the interconnect means its inability to function properly. The two most important functions of the chip interconnect are: Providing connectivity between different parts of design for proper signal propagations (signal circ... » read more

Unifying Hardware-Assisted Verification And Validation Using UVM And Emulation
By Various Writers - 25 Jul, 2013 - Comments: 0

Successful approaches to improve verification productivity are to increase the speed of verification and begin validating software/hardware integration very early in the design process. Historically, verification and validation platforms have been developed as separate flows, preventing reuse of modules and methods between the two. As a consequence, various customized verification and validatio... » read more

New Silos Form In IC Industry
By Ed Sperling - 25 Jul, 2013 - Comments: 0

By Ed Sperling For the past couple of decades corporations around the globe have been focused on down silos. In fact, it has become a mantra. It’s considered essential for making established corporations even more successful, and it’s almost always at the center of turnaround plans for troubled companies. Moreover, across a full spectrum of companies, it’s regularly cited by management c... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy