tag: Mentor Graphics

The Integrated IP Subsystem: A Converging SoC Solution
By Various Writers - 31 Jan, 2013 - Comments: 0

The consumer device market is witnessing incredible market space convergence between mobile handheld, automotive, and home electronics. IP vendors, engineers, and system design engineers face a multitude of challenges when designing and developing ICs, systems, or subsystems for the next great portable device. The next cell phone for instance, will not only be a multimedia player, but also a de... » read more

ESL Challenges
By Ed Sperling - 26 Jan, 2013 - Comments: 0

System-Level Design talks about the challenges of ESL with Cadence's Ran Avinun, Synopsys' Johannes Stahl, Mentor Graphics' Thomas Bollaert and Forte Design Systems' Brett Cline.   [youtube vid=HftMM71Epqo] » read more

Experts At The Table: Latency
By Ed Sperling - 25 Jan, 2013 - Comments: 0

By Ed Sperling Low-Power/High-Performance engineering sat down to discuss latency with Chris Rowen, CTO at Tensilica; Andrew Caples, senior product manager for Nucleus in Mentor Graphics’ Embedded Software Division; Drew Wingard, CTO at Sonics; Larry Hudepohl, vice president of hardware engineering at MIPS; and Barry Pangrle, senior power methodology engineer at Nvidia. What follows are exce... » read more

Reducing The Drama In DFM
By Ed Sperling - 24 Jan, 2013 - Comments: 0

By Ann Steffora Mutschler For reducing cycle time of DFM checks prior to manufacturing, pattern matching is a topic of great excitement as of the past few manufacturing nodes. The idea behind the technology is that there are certain patterns in the physical layout of the chip, which unless they are addressed, won’t come out right. That’s what causes the drama, observed Saleem Haider, se... » read more

Stacked Die From A Networking Angle
By Mark LaPedus - 24 Jan, 2013 - Comments: 1

By Mark LaPedus The first wave of 2.5D chips using silicon interposers are trickling out in the marketplace.FPGA vendor Xilinx was the first chipmaker to ship a 2.5D device, and Altera, Cisco, Huawei and IBM recently have talked about their respective 2.5D chip developments. Generally, Altera and Xilinx have taken a somewhat identical and straightforward approach. The two companies are sepa... » read more

Calibre RealTime: Placing Signoff Verification into the Custom Designer’s Hands
By Various Writers - 24 Jan, 2013 - Comments: 0

How to reduce custom/AMS design cycle time while improving design quality with on-demand, in-design, signoff-quality verification from Calibre RealTime. To download this white paper, click here. » read more

Tradeoffs On The Fly
By Ed Sperling - 17 Jan, 2013 - Comments: 0

By Ann Steffora Mutschler With classical bulk planar technology no longer shrinkable, the industry has been honing in on new ways to continue some scaling, achieve extra speed or better power while minimizing leakage. “To overcome the limits [of bulk planar technology] we need a different solution,” explained Giorgio Cesano, technology R&D marketing director at STMicroelectron... » read more

Embedded Power Management Challenges Grow
By Ed Sperling - 17 Jan, 2013 - Comments: 0

By Ann Steffora Mutschler Power management always has been, and will continue to be, a big issue with electronic devices. But when it comes to power management in embedded systems—controlling battery power in a smartphone, an industrial automation or automotive application, among a myriad of other options—the approaches come with different variables. For example, deeply embedded s... » read more

First Silicon At 14nm
By Ed Sperling - 17 Jan, 2013 - Comments: 0

By Ed Sperling The first 14nm test chips are beginning to roll out the door from foundries, and companies are beginning to trumpet their success. But before anyone pops the champagne corks, there are some caveats. First of all, what most people are billing as 14nm chips are actually mostly 20nm. They are readily willing to concede that point, settling on 16nm, but the reality is that it’s... » read more

All Things To All Customers
By Ed Sperling - 17 Jan, 2013 - Comments: 0

By Ann Steffora Mutschler Low-Power High-Performance Engineering recently spoke with Suresh Menon, VP of systems development at Lattice Semiconductor, about the challenges of directing the development of power-sensitive FPGAs from architectural decisions to identifying the target applications. What follows are excerpts of that discussion. LPHP: When you look at the products that Lattic... » read more

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