tag: Mentor Graphics

The Next UPF
By Erich Marschner - 06 Dec, 2012 - Comments: 0

By Erich Marschner If all goes according to schedule, the new version (2.1) of five-year-old Unified Power Format (UPF) standard will be approved by the IEEE early next year. This is good news, because in the five years since UPF was first defined the demand for systems with both longer battery life and more functionality has increased significantly. As just one example: according to Gartner, ... » read more

To Shrink Or Not To Shrink…And How Much?
By Ed Sperling - 29 Nov, 2012 - Comments: 0

By Ann Steffora Mutschler The 28nm semiconductor manufacturing node is in full swing with 20nm process development ramping quickly. As such, the industry has been looking ahead to the next node shrink to achieve the power, performance and cost advantages that a node shrink promises. However, as we are well aware by now, traditional CMOS planar technology is not scaling as it did in previous ge... » read more

Engineering Change Orders Revisited
By Ed Sperling - 29 Nov, 2012 - Comments: 0

By Ed Sperling The perennial nightmare of the marketing head reporting that a customer will buy a design—but only if it fits into a specific power envelope or has better performance or I/O—is all too familiar to engineering teams. In theory, using more third-party IP should help alleviate this problem because the IP can be changed out relatively easily. The reality, though, is that it�... » read more

Show Me
By Jon McDonald - 29 Nov, 2012 - Comments: 0

By Jon McDonald Many people—engineers especially, myself included—are naturally biased against change. To get an organization to change takes significant energy. This isn’t a new trend. Much of the sentiment of the camp against change can be summed up by referring back to an 1899 quote from Missouri Sen. Willard Vandiver: “… frothy eloquence neither convinces nor satisfies me. I am f... » read more

Questa Covercheck: An Automated Code Coverage Closure Solution
By Various Writers - 29 Nov, 2012 - Comments: 0

This white paper explores the debugging aspect of code coverage closure, and how Questa CoverCheck’s unique ability of formal technology can automatically generate simulation exclusion files to improve code coverage results while reducing the amount of time wasted trying to hit unreachable states. To download this white paper, click here. » read more

Why Do My DP Colors Keep Changing?
By David Abercrombie - 15 Nov, 2012 - Comments: 0

By David Abercrombie At 20nm, foundries are using several different double patterning design flows. One of the more common flows does not actually require the design team to decompose their layers into two colors. The designer only has to verify that the design can be decomposed before taping out each single layer. There are certain obvious advantages to this flow. For example, the designer do... » read more

Reducing IC Cycle Time With Calibre
By Various Writers - 15 Nov, 2012 - Comments: 0

Technology is both a blessing and a curse. The same shrinking of transistor size that has enabled chip designers to place significantly more functionality on the same die area is also responsible for the significant increases we have seen in the number and complexity of verification rules. It would be nice if we could use this phenomenon to our advantage, as an excuse for why our job of physica... » read more

The Growing Integration Challenge
By Ed Sperling - 08 Nov, 2012 - Comments: 0

By Ed Sperling As the number of processors and the amount of memory and IP on a chip continues to skyrocket, so does the challenge for integrating all of this stuff on a single die—or even multiple dies in the same package. There are a number of reasons why it’s getting more difficult to make all of these IP blocks work together. First of all, nothing ever stands still in design. As a r... » read more

Experts At The Table: Issues In Lithography
By Ed Sperling - 05 Nov, 2012 - Comments: 0

By Mark LaPedus Semiconductor Manufacturing & Design sat down to discuss future lithography challenges with Juan Rey, senior director of engineering at Mentor Graphics; Aki Fujimura, chairman and chief executive at D2S; and Tatsuo Enami, general manager for the sales division at Gigaphoton. What follows are excerpts of that conversation. SMD: What is the general state of the next-genera... » read more

Experts At The Table: Issues In Lithography
By Ed Sperling - 29 Oct, 2012 - Comments: 0

By Mark LaPedus Semiconductor Manufacturing & Design sat down to discuss future lithography challenges with Juan Rey, senior director of engineering at Mentor Graphics; Aki Fujimura, chairman and chief executive at D2S; and Tatsuo Enami, general manager for the sales division at Gigaphoton. What follows are excerpts of that conversation. (Part one can be found here.) SMD: Let’s re-vi... » read more

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