Experts At The Table: Issues In Lithography

Last of three parts: EUV’s road map, venture capital, silicon photonics, directed self-assembly, and multipatterning.


By Mark LaPedus
Semiconductor Manufacturing & Design sat down to discuss future lithography challenges with Juan Rey, senior director of engineering at Mentor Graphics; Aki Fujimura, chairman and chief executive at D2S; and Tatsuo Enami, general manager for the sales division at Gigaphoton. What follows are excerpts of that conversation.

SMD: What is the general state of the next-generation lithography (NGL) arena?
Fujimura: I have been in the industry for a long, long time. There have not been this many alternatives that have a chance for success. It’s definitely an interesting time.

SMD: But EUV is clearly late. Does the industry need to allocate more R&D dollars to the various NGL technologies beyond EUV?
Fujimura: Yes. There should be more investment in all areas. Unfortunately, semiconductors in general are not really a fit for a pure venture capital model. It’s too expensive and the returns on any individual bet are not high enough. So it has to be the larger companies that step up and create a fund, or maybe even some kind of joint fund. That’s probably not going to happen. The larger companies may need to collaborate somehow, probably quietly, and voting with their dollars. Don’t just vote on the top one. Vote on several alternatives.
Rey: I agree. I am absolutely convinced that more money is required, because the challenges are bigger. In fact, the need for increased functionality is everywhere. The standard way of actually getting that increased functionality is really becoming a lot more difficult by following the standard path. It is a lot more difficult to do patterning today. There is also a transition toward finFETs, SOI, fully depleted SOI or some other technique. There are other things that are required at the transistor level. It is getting more difficult everywhere.

SMD: What other challenges do you see?
Rey: For example, in the data communications path, there is a need for transmitting more data with lower power and cost. I mentioned silicon photonics because it is a technique that seems to offer the potential for much larger bandwidth for the same amount of power as copper at shorter distances. But no one knows how do to it at a cost that is feasible at this moment. The industry is starting to respond in a very interesting direction. Interestingly enough, the silicon photonics conferences were once attended exclusively by physicists. Now you have keynote presenters from companies like Facebook and Google. So you can see that the large companies that have needs in that direction are paying attention to what’s happening with the technology. The industry as a whole requires more investment from the companies that are getting the benefits of having a path towards more functionality per unit area. Hopefully, they will follow with the funding that is required to bring some of these technologies forward. The industry at a higher level needs to get involved with the technology to enable what customers want.
Fujimura: And let’s take cell phones. For the most part, they still don’t work. You can’t rely on the cell phone to give you a reliable connection. There is a lot more that can be done. We need a lot more and better technology.

SMD: Let’s get back to lithography and EUV. When will EUV finally move into production?
Enami: At the 14nm node in 2016.

SMD: What does Gigaphoton’s EUV source roadmap look like?
Enami: The industry target is to have a 50-watt source in 2015 or so. This is because 2016 is the target for the mass production of DRAMs with EUV. Our milestone, of course, is to reach 50 watts. Our current source is operating at around a few watts. Within this year, we want to achieve 20 watts. In Q1 of next year, we need to reach 50 watts. And if possible, at the end of next year, we want to reach 100 watts. A 100-watt source can produce around 60 to 70 wafers per hour. If we can reach 100 watts by the end of next year, we can provide a source to the customer by 2014 or 2015.

SMD: What’s going on with laser light sources for traditional 193nm lithography?
Enami: We are doing both EUV and deep UV sources. Of course, the laser for DUV is working at the 60-watt level today. That translates to 175 wafers per hour. The recent ASML scanner hopes to reach 200 wafers an hour. That requires 90 watts of power. The actual multi-patterning scanner requires 120 watts in one or two years. We are also developing 120-watt lasers. We’ve almost achieved that target. In production, a 120-watt source power can be applied for 450mm scanners. For deep UV laser sources, multi-patterning requires more R&D dollars. Customer requirements are very tough. Even for DUV lasers, they want cheaper, more durable and higher-availability technologies.

SMD: Do you see other challenges with EUV beyond the source?
Fujimura: EUV needs very accurate masks. If the mask is not accurate, it will show up on the wafer.
Rey: Defects on EUV mask blanks can’t be completely eliminated. That is extremely disruptive. Given that this is the case, what can be done at any part of the design flow to compensate for that? It is possible to find solutions for it. But it is not easy to determine today if there are going to be practical approaches to that. Essentially, you need to know something about the design to be able to use a mask. In this case, you don’t know where the defects are, but you still need to use the mask for that design. That is not something any manager in the food chain wants to deal with. People are starting to scratch their heads about this issue, but nobody seems to be too willing to embrace it. It will be interesting to see how Intel, IBM and TSMC are going to deal with it.

SMD: Will DSA make it into chip production?
Fujimura: I say positively yes.
Rey: I have a positive feeling about DSA. So far, the whole infrastructure that exists today for doing the creation of the shapes for the actual mask seems to be similar. But with DSA, it seems like new models need to be adapted. They need to be proven that they can work in terms of memory consumption, speed and scalability at full-chip level. If you look at it, all of the techniques applied today are essentially based on the resolution limits of photolithography. In the beginning, it was possible to print something very close that was drawn. With the exception of source-mask optimization, pretty much everything follows that key concept. For example, you want to print a rectangle. You start with a rectangle and you see how much you need to modify it. When you apply the model, it predicts how the rectangle is going to be printed. The modifications we’ve seen in DSA are much larger than that.

SMD: Can EUV play a role to help DSA?
Enami: DSA does require guide patterns. To make the guide patterns, you need traditional lithography or EUV.

SMD: If all else fails, the industry can move to multiple patterning. Are EDA tools ready for multiple patterning?
Rey: The tools can be extended. If we go from double patterning to triple patterning, the complexity is a lot larger. But the expectation is that hopefully you won’t need triple patterning everywhere. The algorithms are too complex. There are flow approaches to make the tools feasible. From a conceptual point of view, they are well understood. But not all the tools at full-chip level are completely ready. They are in the process of being developed.

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