tag: Mentor Graphics

The Limits Of Parallelism
By Ann Mutschler - 22 Nov, 2016 - Comments: 0

Parallelism used to be the domain of supercomputers working on weather simulations or plutonium decay. It is now part of the architecture of most SoCs. But just how efficient, effective and widespread has parallelism really become? There is no simple answer to that question. Even for a dual-core implementation of a processor on a chip, results can vary greatly by software application, operat... » read more

Formal’s Roadmap
By Brian Bailey - 22 Nov, 2016 - Comments: 0

Formal verification has come a long way in the past five years as it focused on narrow tasks within the verification flow. Semiconductor Engineering sat down to discuss that progress, and the future of formal technologies, with [getperson id="11306" comment="Raik Brinkmann"], president and CEO of [getentity id="22395" e_name="OneSpin Solutions"]; Harry Foster, chief verification scientist at [g... » read more

New Wave Of Consolidation
By Ed Sperling - 22 Nov, 2016 - Comments: 0

Consolidation is picking up again across the semiconductor industry, against a backdrop of looming interest rate hikes, geopolitical uncertainty, and the erosion of longstanding demarcations between markets. In the past couple of weeks, Siemens signed a deal to buy [getentity id="22017" e_name="Mentor Graphics"] for $4 billion, and [getentity id="22865" e_name="Samsung"] purchased Harman, a ... » read more

The Week In Review: Design
By Jesse Allen - 18 Nov, 2016 - Comments: 0

M&A Siemens plans to buy Mentor Graphics for $4.5 billion in cash. The move, if approved by regulators, would greatly expand Siemens’ capabilities in multi-physics design and embedded software for everything from semiconductors to automotive wiring harnesses. The transaction is expected to close in the second quarter of 2017. Tools Mentor Graphics uncorked a new product to measur... » read more

More EUV Mask Gaps
By Mark LaPedus - 17 Nov, 2016 - Comments: 12

Extreme ultraviolet (EUV) lithography is at a critical juncture. After several delays and glitches, [gettech id="31045" comment="EUV"] is now targeted for 7nm and/or 5nm. But there are still a number of technologies that must come together before EUV is inserted into mass production. And if the pieces don’t fall into place, EUV could slip again. First, the EUV source must generate more ... » read more

Fill/Cut Self-Aligned Double-Patterning
By David Abercrombie - 17 Nov, 2016 - Comments: 0

By David Abercrombie, Rehab Ali, Ahmed Hamed-Fatehy, and Shetha Nolke Self-aligned double patterning (SADP) is an alternative double-patterning process to the traditional litho-etch-litho-etch (LELE) approach used in most advanced production nodes. The main difference between the two approaches is that in LELE, the layout is divided between two masks, and the second mask is aligned with resp... » read more

Mastering The Magic Of Multi-Patterning
By Mentor, a Siemens Business - 17 Nov, 2016 - Comments: 0

Multi-patterning technology was introduced at the 20 nm node to overcome lithographic limitations in current IC manufacturing processes. While processes like double and triple patterning may sometimes seem like magic, successfully implementing multi-patterning compliance in the IC design and verification flow requires a thorough understanding of multi-patterning techniques and their impact on y... » read more

Why EUV Is So Difficult
By Mark LaPedus - 17 Nov, 2016 - Comments: 23

For years, extreme ultraviolet (EUV) lithography has been a promising technology that was supposed to help enable advanced chip scaling. But after years of R&D, EUV is still not in production despite major backing from the industry, vast resources and billions of dollars in funding. More recently, though, [gettech id="31045" comment="EUV"] lithography appears to be inching closer to pos... » read more

Teaching Computers To See
By Ann Mutschler - 16 Nov, 2016 - Comments: 0

Vision processing is emerging as a foundation technology for a number of high-growth applications, spurring a wave of intensive research to reduce power, improve performance, and push embedded vision into the mainstream to leverage economies of scale. What began as a relatively modest development effort has turned into an all-out race for a piece of this market, and for good reason. Mark... » read more

Blog Review: Nov. 16
By Jesse Allen - 16 Nov, 2016 - Comments: 0

Cadence's Paul McLellan highlights a talk from the recent Jasper User Group by ARM's Daryl Stewart on how the company saw the value of formal verification. Synopsys' Patrick Sheridan looks at the benefits of using SystemC TLM-2.0 AT for virtual prototype architecture modeling. Mentor's Jim Martens argues for the importance of a reliable power delivery network. A Lam Research staff writ... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy