Simulation Performance Driven By Model Efficiency


In real estate it’s all about location, location, location. For system level simulation it’s all about performance, performance, performance. I have heard many opinions on the performance of SystemC and TLM simulations: some positive, some negative, much of the opinion based on hearsay or other unreliable information. I believe the performance of the simulation is mainly driven by the model... » read more

Blog Review: Jan. 28


Mentor Graphics' John Day points to the growing presence of automakers in Silicon Valley. The latest émigré is Ford, which is setting up a research and innovation center in Palo Alto, but the company is hardly alone. Electronics could well become the real differentiators in vehicles. ARM's Andrew Sloss points to an intriguing relationship between data and economic growth—not to mention m... » read more

A Complete Analog Design Flow For Verification Planning And Requirement Tracking


Verifying designs to meet all specifications across all process corners has become an intractable problem from the perspective of debugging, managing, tracking, and meeting verification goals. Implementing a CDV methodology for analog designs can evolve analog design and verification to a standard process-based method that can be tracked and its progress measured. This paper aims to extend comm... » read more

New Challenges For Wearables


The earliest recorded mention of a wristwatch dates back to the late 1500s, but it really began gaining adherents in Great Britain’s Boer War campaign as a way of synchronizing military actions beyond the line of sight. Strapping a pocket watch to a horse or a camel simply didn’t work, and pulling it out of a jacket pocket was not only inconvenient, it was dangerous. Advertised as a “c... » read more

The Danger of Using Patents


As I have written about recently, [getkc id="30" kc_name="emulation"] is a hot topic for EDA and the number and length of lawsuits related to the technology is almost overwhelming. The latest phase has just concluded with a summary judgment against [getentity id="22035" e_name="Synopsys"] on Jan. 20. It all started in late 2012 when Synopsys, which had just acquired [getentity id="22738" e_nam... » read more

Week 33: Changes To The DAC Show Floor


At this point in my blogging/vlogging career I’m assuming I have an audience of thousands who hang on my every word. But the few of you left (okay, so this is tongue in cheek… I have in fact seen the number of YouTube views!) who have not seen my DAC TV interview with Brian Fuller (below) need to know that we are changing DAC exhibit hours and moving the evening receptions on Monday and Tue... » read more

The Week In Review: Design/IoT


Legal A U.S. District Court invalidated three patents related to emulation, which were part of a patent infringement lawsuit filed by Synopsys against Mentor Graphics. The fourth patent will be reviewed by the U.S. Patent Trial and Appeal Board. Synopsys said it is evaluating an appeal and criticized the decision. "Synopsys strongly disagrees with the court's decision," said a Synopsys spokesp... » read more

Manufacturing And Packaging Changes For 2015


This year more than 26 people provided predictions for 2015. Most of these came from the EDA industry, so the results may be rather biased. However, ecosystems are coming closer together in many parts of the semiconductor food chain, meaning that the EDA companies often can see what is happening in dependent industries and in the system design houses. Thus their predictions may have already res... » read more

Rule Deck Comparison Doesn’t Have To Be Difficult


Foundry rule decks change all the time, as foundries uncover new manufacturing issues, or the process changes, or design criteria are tightened to improve runtime or stability. Sometimes new versions of a user’s design rule checking (DRC) tool are released, and the results from the DRC run differ from the previous version. Or perhaps a company wants to compare results between rule decks from ... » read more

EDT Test Points


Embedded test compression was commercially introduced over a decade ago and has scaled to well beyond the 100X range envisioned when it was first introduced. However, growing gate counts enabled by new technology nodes as well as new fault models targeting defects within standard cells are driving the need for even greater compression levels. This paper describes an exciting new technology, cal... » read more

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