tag: Mentor

EDA On Cloud Presents Unique Challenges
By Ann Mutschler - 31 Mar, 2022 - Comments: 0

Discussions about cloud-based EDA tools are heating up for both hardware and software engineering projects, opening the door to vast compute resources that can be scaled up and down as needed. Still, not everyone is on board with this shift, and even companies that use the cloud don't necessarily want to use it for every aspect of chip design. But the number of cloud-based EDA tools is growi... » read more

Clocks Getting Skewed Up
By Brian Bailey - 30 Mar, 2022 - Comments: 0

At a logical level, synchronous designs are very simple and the clock just happens. But the clocking network is possibly the most complex in a chip, and it's fraught with the most problems at the physical level. To some, the clock is the AC power supply of the chip. To others, it is an analog network almost beyond analysis. Ironically, there are no languages to describe clocking, few tools t... » read more

Blog Review: March 30
By Jesse Allen - 30 Mar, 2022 - Comments: 0

Ansys' Shawn Carpenter takes a look at the continuing impact of potential interference with aircraft's radar altimeters on the roll out of the 5G C-band and the testing that will be needed to enable 5G C-band service towers to begin operating near airports by July. Siemens' Harry Foster points to an increase in the number of engineers working on automotive ASIC projects and the growing compl... » read more

Improving Memory Efficiency And Performance
By Bryon Moyer - 28 Mar, 2022 - Comments: 0

This is the second of two parts on CXL vs. OMI. Part one can be found here. Memory pooling and sharing are gaining traction as ways of optimizing existing resources to handle increasing data volumes. Using these approaches, memory can be accessed by a number of different machines or processing elements on an as-needed basis. Two protocols, CXL and OMI, are being leveraged to simplify thes... » read more

Incremental Design Breakdown
By Brian Bailey - 24 Mar, 2022 - Comments: 0

For the past two decades, most designs have been incremental in nature. They heavily leveraged IP used in previous designs, and that IP often was developed by third parties. But there are growing problems with that methodology, especially at advanced nodes where back-end issues and the impact of 'shift left' are reducing the savings from reuse. The value of IP reuse has been well established... » read more

How To Justify A Data Center
By Ann Mutschler - 24 Mar, 2022 - Comments: 0

The breadth of cloud capabilities and improvements in cost and licensing structures is prompting chipmakers to consider offloading at least some of their design work into the cloud. Cloud is a viable business today for semiconductor design. Over the past decade, the interest in moving to cloud computing has grown from an idea that was fun to talk about — but which no one was serious about ... » read more

The Value Of RF Harmonic Balance Analyses For Analog Verification
By Pradeep Thiagarajan - 24 Mar, 2022 - Comments: 0

By Pradeep Thiagarajan and Scott Guyton The world we live in is intricately connected by electronic systems that are expected to function flawlessly to satisfy consumer needs. Functionality violations beyond certain tolerance levels are frowned upon and negatively impact the quality level of products. These systems are required to function accurately, in tandem with other interdependent syst... » read more

Siemens EDA’s Full-Flow Portfolio Helps Engineers Achieve Optimum IC Design Verification Efficiency
By Siemens EDA - 24 Mar, 2022 - Comments: 0

A quick overview of the front-end flow using the S-Edit schematic capture environment will be covered in this white paper, followed by a more detailed description and steps for using the Analog FastSPICE (AFS) platform simulator to go through the verification of a basic amplifier design. Greater efficiency in analog design verification can now be achieved using our enhanced inter-tool commun... » read more

Blog Review: March 23
By Jesse Allen - 23 Mar, 2022 - Comments: 0

Arm's Ilias Vougioukas presents new ways to improve on virtual to physical memory translation without breaking any of the pre-existing hardware or software. Siemens' Scot Morrison considers the current regulatory landscape for security of medical devices, including how device manufactures need to proactively implement a plan to find, assess, and respond to potential vulnerabilities. Synop... » read more

CXL and OMI: Competing or Complementary?
By Bryon Moyer - 23 Mar, 2022 - Comments: 1

System designers are looking at any ideas they can find to increase memory bandwidth and capacity, focusing on everything from improvements in memory to new types of memory. But higher-level architectural changes can help to fulfill both needs, even as memory types are abstracted away from CPUs. Two new protocols are helping to make this possible, CXL and OMI. But there is a looming question... » read more

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