tag: Mentor

From Tool Agents To Flow Agents
By Brian Bailey - 30 Apr, 2025 - Comments: 0

Experts At The Table: AI is starting to impact several parts of the EDA design and verification flows, but so far these improvements are isolated to single tool or small flows provided by a single company. What is required is a digital twin of the development process itself on which AI can operate. Semiconductor Engineering sat down with a panel of experts to discuss these issues and others, in... » read more

Blog Review: Apr. 30
By Jesse Allen - 30 Apr, 2025 - Comments: 0

Cadence’s Sree Parvathy points out how electrothermal analysis can help designers understand how temperature changes affect device behavior, such as mobility, threshold voltage, and saturation to mitigate potential failures due to thermal overstress. In a podcast, Siemens’ Conor Peick, Dale Tutt, and Mike Ellow chat about the transition towards software-defined products and why companies... » read more

Security Power Requirements Are Growing
By Adam Kovac - 28 Apr, 2025 - Comments: 0

Determining how much power to budget for security in a chip design is a complex calculation. It starts with a risk assessment of the cost of a breach and the number of possible attack vectors, and whether security is active or passive. Different forms of root of trust and cryptography have different power costs. Different systems could require tradeoffs between performance and security, whic... » read more

AI Drives Re-Engineering Of Nearly Everything In Chips
By Ed Sperling - 24 Apr, 2025 - Comments: 0

AI's ability to mine patterns across massive quantities of data is causing fundamental changes in how chips are used, how they are designed, and how they are packaged and built. These shifts are especially apparent in high-performance AI architectures being used inside of large data centers, where chiplets are being deployed to process, move, and store massive amounts of data. But they also ... » read more

Reap Rewards With Shift-Left Pattern Matching For Custom And AMS Designs
By John Muirhead - 24 Apr, 2025 - Comments: 0

To keep up with the growing complexities of IC design, major semiconductor companies are adopting shift-left strategies. For verification, this means pulling much of the work into the physical design stage. By moving critical checks earlier in the design cycle, you can identify and resolve issues before they escalate, streamlining the overall development process. The Calibre tools have been ... » read more

New Ways To Improve EDA Productivity
By Ann Mutschler - 24 Apr, 2025 - Comments: 0

EDA vendors are taking aim at new ways to improve the productivity of design and verification engineers, who are struggling to keep pace with exponential increases in chip complexity in tight time-to-market windows and with constrained engineering talent pipelines. In the past, progress often was as straightforward as improving algorithms or parallelizing computations in a linear flow. But w... » read more

Analog Creates Ripples in Digital Verification
By Brian Bailey - 24 Apr, 2025 - Comments: 0

We live in an analog world, but analog has been minimized whenever possible. At some point digital and analog must come together in every electronic device, and that has long been an area where errors creep in. The Wilson Research Group and Siemens EDA functional verification study has long shown that analog and mixed signal are two of the highest causes of flaws that result in chip respins.... » read more

Need For Speed Drives Targeted Testing
By Gregory Haley - 23 Apr, 2025 - Comments: 0

As packaging complexity increases and nodes shrink, defect detection becomes significantly more difficult. Engineers must contend with subtle variations introduced during fabrication and assembly without sacrificing throughput. New material stacks degrade signal-to-noise ratios, which makes metrology more difficult. At the same time, inspection systems face a more nuanced challenge — how t... » read more

Chip Industry Week In Review
By The SE Staff - 18 Apr, 2025 - Comments: 0

[Podcast version is here.] TSMC said it will produce 30% of its leading-edge chips in Arizona when all six of its fabs are operational, a total investment of $165 billion, Axios reported. In its latest SEC filing, the foundry said it continues to add capacity in Taiwan, Arizona, Japan, and Germany. The Trump administration launched a Section 232 investigation into semiconductors and relat... » read more

Blog Review: Apr. 16
By Jesse Allen - 16 Apr, 2025 - Comments: 0

Siemens’ Tova Levy finds that heterogeneous integration necessitates a shift to a system-level technology co-optimization approach where power, performance, area, cost, and reliability are considered across various components, including silicon, package, interposer, and PCB. Synopsys’ Greg Sorber listens in as Arm’s Rene Haas and Synopsys’ Sassine Ghazi discuss the opportunity for AI... » read more

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