Tackling Reliability In Early IC Design


As the semiconductor industry continues its relentless march towards smaller process nodes and more complex integrated circuits (ICs), the challenge of ensuring reliability has become increasingly difficult. Industry analysts predict a significant increase in demand for semiconductor reliability verification as analysis become critical parts of the overall design verification process. The st... » read more

Blog Review: Jan. 8


Cadence's Igor Krause unravels the different Orthogonal Header Content (OHC) types in PCIe 6.0, which work as an extra header for the Transaction Layer Packet (TLP) that incorporates information fields that are needed depending on the TLP type. Siemens EDA's Yunhong Min considers how AI and machine learning are reshaping functional verification workflows from translating specifications to de... » read more

Chip Industry Week In Review


Updated for 12/20 government fundings and 12/23 for China trade investigation announcements. President Biden announced a trade investigation into "China's unfair trade practices in the semiconductor sector."  The announcement stated "PRC semiconductors often enter the U.S. market as a component of finished goods. This Section 301 investigation will examine a broad range of the PRC’s non-m... » read more

Calibre DesignEnhancer Design-Stage Layout Modification Improves Power Management Faster And Earlier


In today’s IC designs, effective power management through layout optimization is crucial for achieving PPA targets. This paper, written by Jeff Wilson, describes how the Calibre DesignEnhancer platform, is used to specifically tackle the EMIR components of power management. DesignEnhancer offers P&R and custom/analog design teams a fast, integrated environment for implementing Calibre-cle... » read more

Strain, Stress In Advanced Packages Drives New Design Approaches


Thermal and mechanical stresses are creating significant challenges in heterogeneous chiplet assemblies, increasing the time and cost required to work through all the possible physical effects, dependencies, and interactions, and driving demand for new tools. Unlike in the past, when various components were crammed into a planar SoC on a relatively thick substrate, the new substrates are bei... » read more

Enhancing Power Reliability Through Design-Stage Layout Optimization


As integrated circuit (IC) designs continue to scale, the demand for efficient power management, performance optimization and reliable physical layout modification grows more critical. Meeting these power, performance and area (PPA) targets is essential for ensuring that IC designs operate effectively at advanced process nodes. One of the main challenges for design and verification engineers is... » read more

Improving Verification Performance


Without methodology improvements, verification teams would not be able keep up with the growing complexity and breadth of the tasks assigned to them. Tools alone will not provide the answer. The magnitude of the verification task continues to outpace the tools, forcing design teams to seek out better ways to intermix and utilize the tools that are available. But as verification teams take on... » read more

SLM Evolves Into Critical Aspect Of Chip Design And Operation


Silicon lifecycle management has evolved greatly in the past five years, moving from novel concept to a key part of design flows at industry leaders such as NVIDIA, Amazon Web Services, Ericsson, and others. Along with becoming a major focus for companies developing semiconductors, the use cases have expanded. While initially focused on post-silicon insights, SLM has expanded to cover the en... » read more

Blog Review: Dec. 18


Siemens’ Michael Munsey predicts that the convergence of AI, advanced packaging, and rise of software-defined products aren’t just incremental changes but will represent a fundamental shift in how we think about semiconductor design and manufacturing. Cadence's Veena Parthan points to hex-core voxels as a significant leap forward for the CFD meshing process that blends the best of struct... » read more

RISC-V Profiles Help Conformance


Experts At The Table: What's needed to be able to trust that a RISC-V implementation will work as expected across multiple designs using standard OSes. Semiconductor Engineering discussed the issue with John Min, vice president of customer service at Arteris; Zdeněk Přikryl, CTO of Codasip; Neil Hand, director of marketing at Siemens EDA (at the time of this discussion); Frank Schirrmeist... » read more

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