tag: Mentor

EU Chips Act: A Game Changer For The Digital Economy
By Maria Daniela Perez - 17 Dec, 2024 - Comments: 0

The global semiconductor landscape has undergone significant transformation in recent years. With disruptions such as the semiconductor supply chain crisis and the challenges it posed to the automotive sector, Europe’s dependence on external fabrication facilities, particularly in Taiwan, has become a pressing concern. In response, the European Union (EU) introduced the EU Chips Act, a compre... » read more

Chip Industry Week In Review
By The SE Staff - 13 Dec, 2024 - Comments: 0

The 2024 IEEE International Electron Devices Meeting (IEDM) was held this week, prompting a number of announcements from: imec: Proposed a new CFET-based standard cell architecture for the A7 node containing two rows of CFETs with a shared signal routing wall in between, allowing standard cell heights to be reduced from 4 to 3.5T, compared to single-row CFETs. Integrated indium pho... » read more

Addressing Reset Tree Design Challenges For Complex SoCs With Advanced Structural Checks
By Reetika - 12 Dec, 2024 - Comments: 0

As SoC designs continue to evolve, the complexity of reset architectures has grown significantly. Traditionally, clock tree synthesis has been a major focus due to timing challenges, but now reset trees demand equal attention. With multiple reset sources, designers must deal with reset trees that can be more intricate than clock trees. Errors within a reset tree can lead to serious issues, incl... » read more

Is In-Memory Compute Still Alive?
By Bryon Moyer - 12 Dec, 2024 - Comments: 1

In-memory computing (IMC) has had a rough go, with the most visible attempt at commercialization falling short. And while some companies have pivoted to digital and others have outright abandoned the technology, developers are still trying to make analog IMC a success. There is disagreement regarding the benefits of IMC (also called compute-in-memory, or CIM). Some say it’s all about reduc... » read more

Chiplet Interconnects Add Power And Signal Integrity Issues
By Adam Kovac - 12 Dec, 2024 - Comments: 0

The flexibility and scalability offered by chiplets make them an increasingly attractive choice over planar SoCs, but the rollout of increasingly heterogeneous assemblies adds a variety of new challenges around the processing and movement of data. Nearly all of the chiplets in use today were designed in-house by large systems companies and IDMs. Going forward, third-party chiplets will begin... » read more

Where Is The Software For Shift Left?
By Brian Bailey - 12 Dec, 2024 - Comments: 0

Co-development of hardware and software has been a dream for a long time, but significant hurdles remain. Neither domain is ready with what the other requires at the appropriate time. The earlier something can be done in a development flow, the less likely problems will be found when they are more difficult or expensive to fix. It may require both tool and methodology changes, so that a proc... » read more

Why Chips Fail, And What To Do About It
By Ed Sperling - 11 Dec, 2024 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss reliability of chips in the context of safety- and mission-critical systems, as well as increasing utilization due to an explosion in AI data, with Steve Pateras, vice president of marketing and business development at Synopsys; Noam Brousard, vice president of solutions engineering at proteanTecs; Harry Foster, chief verificat... » read more

Verifying SRAM Yield Inclusive Of Rare And Random Defects
By Siemens EDA - 11 Dec, 2024 - Comments: 0

Large disparities were observed between wafer level SRAM Access Disturb related bit-fails as measured on silicon wafers and the number of such bit-fails as predicted by intrinsic device variability alone. Root cause investigations pointed to a rare but random defect lowering threshold voltage of the NFET devices of the SRAM bit-cell. This work presents a novel method to enable the inclusion of ... » read more

Silicon Lifecycle Management Gains Steam
By Laura Peters - 10 Dec, 2024 - Comments: 0

Silicon lifecycle management (SLM) is gaining significant traction, driven increasingly by stringent reliability requirements for safety-critical devices in aerospace, medical, and automotive. Improving reliability has been a discussion point for years, but it has become especially important with the use of chips designed at leading-edge nodes in both mission- and safety-critical application... » read more

ESD Verification For 2.5D And 3D-ICs
By Siemens EDA - 10 Dec, 2024 - Comments: 0

Ensuring your integrated circuit (IC) design can withstand electrostatic discharge (ESD) events without incurring damage or failure is an extremely important activity in IC circuit design and verification. While automated flows for ESD verification are well-established for regular 2D ICs, 2.5D and 3D integration presents new challenges in both ESD design and verification. The new automated ESD ... » read more

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