tag: Mentor

Voltage Drop Now Requires Dynamic Analysis
By Karen Heyman - 08 Aug, 2024 - Comments: 0

At one time a relatively infrequent occurrence, voltage drop is now a major impediment to reliability at advanced nodes. Decades ago, voltage drop was only an issue for very large and high-speed designs, where there was concern about supply lines delivering full voltage to transistors. As design margins have tightened in modern advanced designs, controlling voltage drop has become a requiremen... » read more

Blog Review: Aug. 7
By Jesse Allen - 07 Aug, 2024 - Comments: 1

Synopsys' Jyotika Athavale and Randy Fish investigate the problem of silent data corruption caused by difficult-to-detect hardware defects that cause unnoticed errors in the data being processed and is becoming an increasingly pressing problem as computing scales massively at a rapid pace with the demands of AI. Siemens' Keith Felton suggests adopting physical design reuse circuits to provid... » read more

Focus Shifts To Application-Specific Workloads
By Ann Mutschler - 07 Aug, 2024 - Comments: 0

Experts At The Table: EDA has undergone numerous workflow changes over time. Different skill sets have come into play over the years, and at times this changed the definition of what it means to design at the system level. To work out what this means for designers today, and how it looks going forward, Semiconductor Engineering sat down with Michal Siwinski, chief marketing officer at Arteris; ... » read more

AI/ML’s Role In Design And Test Expands
By Laura Peters - 06 Aug, 2024 - Comments: 1

The role of AI and ML in test keeps growing, providing significant time and money savings that often exceed initial expectations. But it doesn't work in all cases, sometimes even disrupting well-tested process flows with questionable return on investment. One of the big attractions of AI is its ability to apply analytics to large data sets that are otherwise limited by human capabilities. In... » read more

Ensure Reliability In Automotive ICs By Reducing Thermal Effects
By Lee Wang - 05 Aug, 2024 - Comments: 0

In the relentless pursuit of performance and miniaturization, the semiconductor industry has increasingly turned to 3D integrated circuits (3D-ICs) as a cutting-edge solution. Stacking dies in a 3D assembly offers numerous benefits, including enhanced performance, reduced power consumption, and more efficient use of space. However, this advanced technology also introduces significant thermal di... » read more

Chip Industry Week in Review
By The SE Staff - 02 Aug, 2024 - Comments: 0

Okinawa Institute of Science and Technology proposed a new EUV litho technology using only four reflective mirrors and a new method of illumination optics that it claims will use 1/10 the power and cost half as much as existing EUV technology from ASML. Applied Materials may not receive expected U.S. funding to build a $4 billion research facility in Sunnyvale, CA, due to internal government... » read more

Chip Security Now Depends On Widening Supply Chain
By Ann Mutschler - 01 Aug, 2024 - Comments: 0

Securing chips is becoming more challenging as SoCs are disaggregated into chiplets, creating new vulnerabilities that involve hardware and software, as well as multiple entities, and extending threats across a much broader supply chain. In the past, much of the cyber threat model was confined to either hardware or software, and where multiple vendors were involved, various chips were separa... » read more

Defining Chip Threat Models To Identify Security Risks
By Adam Kovac - 01 Aug, 2024 - Comments: 0

Experts At The Table: As hardware weaknesses have become a major target for attackers, the race to find new ways to strengthen chip security has begun to heat up. But one-size does not fit all solution. To figure out what measures need to be taken, a proper threat model must be assessed. Semiconductor Engineering sat down with a panel of experts at the Design Automation Conference in San Franci... » read more

Where Power Savings Really Count
By Ed Sperling - 31 Jul, 2024 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss why and where improvements in architectures and data movement will have the biggest impact, with Hans Yeager, senior principal engineer, architecture, at Tenstorrent; Joe Davis, senior director for Calibre interfaces and EM/IR product management at Siemens EDA; Mo Faisal, CEO of Movellus; Trey Roessig, CTO and senior vice presi... » read more

Blog Review: July 31
By Jesse Allen - 31 Jul, 2024 - Comments: 0

Cadence's Jasmine Makhija explains how to boost the performance of CXL 3.0 by using NOP (No Operation) Insertion Hints in latency-optimized 256B Flit Mode, which enables the system to quickly revert to the low-latency path after temporarily switching to a higher-latency path due to error correction needs. Synopsys' Robert Fey finds that by automatically and dynamically linking requirements a... » read more

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