Chip Industry Week In Review


China's Hefei Lumiverse Technology reportedly has developed a desktop-sized High Harmonic Generation light source that generates wavelengths as small as 1nm. One customer already has used it to produce 14nm chips, which was the original target node for EUV, according to one report. As a point of comparison, TSMC and Samsung didn't start using EUV until the 7nm node, relying instead on immersion... » read more

The Future For Formal Verification


Experts at the table: Semiconductor Engineering sat down to discuss possible future directions for formal verification technology with Ashish Darbari, CEO for Axiomise; Jin Zhang, product management group director for the Verification Group at Cadence; Sean Safarpour, executive director for R&D at Synopsys; and Jeremy Levitt, principal engineer for Digital Verification Technology at Siemen... » read more

Blog Review: Nov. 19


Cadence's Mamta Rana explores how Forward Error Correction in PCIe 6.0 is key to its 64.0 GT/s per lane bandwidth by enabling the receiver to detect and correct errors without retransmissions or protocol-level recovery by adding redundant information to transmitted data. Siemens' Dave Rich shares a paper from DVCon 1992 that introduced a new RTL modeling construct to Verilog, eventually know... » read more

Edge AI Is Starting To Transform Industrial IoT


A slew of wireless and increasingly multi-modal sensors is being targeted at the Industrial Internet of Things (IIoT), setting the stage for significant improvements in efficiency, higher yield, and reduced downtime. Wired IIoT devices, such as smart energy meters and breakers, industrial network gateways, and environmental sensors already are well established in factory settings. They have ... » read more

Noise: A Chip Killer


Noise has always been important to communications experts, but it's quickly becoming an issue that every semiconductor designer has to contend with. Some chips already have been compromised. Noise can be defined as any deviation from the ideal that can impact intended functionality. When it comes to semiconductors, that could mean the ability to reliably extract a signal value at the intende... » read more

Power Integrity And Voltage Issues Get Harder To Detect And Solve


Voltage and power integrity are becoming increasingly critical and challenging for chip designers and architects, regardless of which process technology they are using or which market they are targeting. An explosion of features vying unevenly for current is increasing the number of constraints and possible interactions that engineers need to sort through to ensure reliability. These include... » read more

Accellera Standard Supports Hierarchical Data Model For CDC And RDC Analysis


The hierarchical flow for clock domain crossing (CDC) and reset domain crossing (RDC) is a methodology used in the verification of large, complex digital integrated circuits. It's a divide-and-conquer approach that significantly improves the efficiency and turnaround time for ensuring design reliability against metastability and other issues at asynchronous boundaries. Questa CDC and RDC sol... » read more

Standardization Of HDMs For Hierarchical CDC And RDC Analysis


Currently hierarchical data models (HDM) must be generated with the same EDA tool that customers will use to consume the HDM for CDC and RDC analysis at the SoC level. To resolve this problem a CDC Working Group was created within the Accellera organization. The goal of this Working Group is to create a standard format for HDMs so the models can be consumed by any EDA tool irrespective of the s... » read more

Keeping The Lights On: How Digital Twins And Smart Semiconductor Management Power Our 24/7 World


Hey there, tech enthusiasts and digital pioneers! Have you ever stopped to think about the tiny, intricate components that keep our modern world humming? From the advanced safety features in your car to the massive data centers powering AI, semiconductors are truly the unsung heroes. But what happens when these tiny titans face immense pressure, like the non-stop demands of AI workloads? That's... » read more

AI In Test Analytics: Promise Vs. Reality


The semiconductor industry is increasingly turning to artificial intelligence as the solution for increasing complexity in test analytics, hoping algorithms can tame the growing flood of production data. The need to extract actionable insight from that torrent is pressing. AI/ML (AI) models promise to find correlations buried in multidimensional datasets, predict failures before they occur, and... » read more

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