Metal Oxide Resist (MOR) EUV Lithography Processes For DRAM Application

By TEL - 19 Oct, 2022 - Comments: 0

This paper reports the readiness of key EUV resist process technologies using Metal Oxide Resist (MOR) aiming for the DRAM application. For MOR, metal contamination reduction and CD uniformity (CDU) are the key performance requirements expected concerning post exposure bake (PEB). Based on years of experience with spin-on type Inpria MOR, we have designed a new PEB oven to achieve contamination... » read more

Nanosheet FETs Drive Changes In Metrology And Inspection

By Karen Heyman - 09 Aug, 2022 - Comments: 0

In the Moore’s Law world, it has become a truism that smaller nodes lead to larger problems. As fabs turn to nanosheet transistors, it is becoming increasingly challenging to detect line-edge roughness and other defects due to the depths and opacities of these and other multi-layered structures. As a result, metrology is taking even more of a hybrid approach, with some well-known tools moving... » read more

High-NA EUV May Be Closer Than It Appears

By Katherine Derbyshire - 16 Jun, 2022 - Comments: 1

High-NA EUV is on track to enable scaling down to the Angstrom level, setting the stage for chips with even higher transistor counts and a whole new wave of tools, materials, and system architectures. At the recent SPIE Advanced Lithography conference, Mark Phillips, director of lithography hardware and solutions at Intel, reiterated the company’s intention to deploy the technology in high... » read more

Strategies For Faster Yield Ramps On 5nm Chips

By Laura Peters - 12 Apr, 2022 - Comments: 0

Leading chipmakers TSMC and Samsung are producing 5nm devices in high volume production and TSMC is forging ahead with plans for first 3nm silicon by year end. But to meet such aggressive targets, engineers must identify defects and ramp yield faster than before. Getting a handle on EUV stochastic defects — non-repeating patterning defects such as microbridges, broken lines, or missing con... » read more

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tag: metal oxide resists

Metal Oxide Resist (MOR) EUV Lithography Processes For DRAM Application

Nanosheet FETs Drive Changes In Metrology And Inspection

High-NA EUV May Be Closer Than It Appears

Strategies For Faster Yield Ramps On 5nm Chips