Chip Industry Week In Review

By The SE Staff - 10 Jan, 2025 - Comments: 0

Global semiconductor sales hit $57.8 billion in November 2024, an increase of 20.7% compared to the same month last year, according to the Semiconductor Industry Association. In U.S. government news: The U.S. Department of Commerce finalized up to $325 million in CHIPS Act funding for Hemlock Semiconductor, which will support construction of a new semiconductor-grade polysilicon manufac... » read more

Chip Industry Week in Review

By The SE Staff - 03 Jan, 2025 - Comments: 0

Lawrence Livermore National Laboratory is ramping up R&D for next-gen EUV and plasma-based particle sources, aiming to increase the EUV laser source power by an order of magnitude while also making it more energy-efficient. Specifically, the goal is to replace today's CO2-based laser with a solid-state laser, using a thulium-doped yttrium lithium fluoride medium to increase the laser's powe... » read more

CXL’s Potential to Elevate The Capabilities of HPC and AI Applications (Micron, Intel)

By Technical Paper Link - 20 Dec, 2024 - Comments: 0

A new technical paper titled "Optimizing System Memory Bandwidth with Micron CXL Memory Expansion Modules on Intel Xeon 6 Processors" was published by researchers at Micron and Intel. Abstract "High-Performance Computing (HPC) and Artificial Intelligence (AI) workloads typically demand substantial memory bandwidth and, to a degree, memory capacity. CXL memory expansion modules, also known... » read more

Chip Industry Week In Review

By The SE Staff - 13 Dec, 2024 - Comments: 0

The 2024 IEEE International Electron Devices Meeting (IEDM) was held this week, prompting a number of announcements from: imec: Proposed a new CFET-based standard cell architecture for the A7 node containing two rows of CFETs with a shared signal routing wall in between, allowing standard cell heights to be reduced from 4 to 3.5T, compared to single-row CFETs. Integrated indium pho... » read more

Luminary Panel Sees Multi-Beam Mask Writers And Curvilinear Masks Key To 193i And EUV

By Jan Willis - 24 Oct, 2024 - Comments: 0

Attendance was up and the mood was optimistic at this year’s SPIE Photomask and EUV conference held September 29 through October 3, 2024. The optimism was apparent as well for multi-beam mask writers and curvilinear masks during the eBeam Initiative’s 15th annual reception and meeting held on October 1. In the eBeam Initiative’s annual Luminaries survey, 93% of those surveyed said that pu... » read more

Blog Review: Aug. 21

By Jesse Allen - 21 Aug, 2024 - Comments: 0

Cadence's Reela Samuel explores the critical role of PCIe 6.0 equalization in maintaining signal integrity and solutions to mitigate verification challenges, such as creating checkers to verify all symbols of TS0, ensuring the correct functioning of scrambling, and monitoring phase and LTSSM state transitions. Siemens' John McMillan introduces an advanced packaging flow for Intel's Embedded ... » read more

CD Spec For Curvilinear Masks

By D2S - 23 Jul, 2024 - Comments: 0

Within the photomask industry, there's a major transformation from conventional Manhattan masks to more advanced curvilinear masks. Researchers from D2S and Micron Technology propose an equivalent CD spec for the curvy masks and use this spec to show that curvy masks have smaller mask variations than Manhattan masks. Find the technical paper here. Published June 2024. Linyong (Leo) Pang, ... » read more

Memory System Benchmarking, Simulation, And Application Profiling Via A Memory Stress Framework

By Technical Paper Link - 22 May, 2024 - Comments: 0

A technical paper titled “A Mess of Memory System Benchmarking, Simulation and Application Profiling” was published by researchers at Barcelona Supercomputing Center, Unversitat Politecnica de Catalunya, and Micron Technology (Italy). Abstract: "The Memory stress (Mess) framework provides a unified view of the memory system benchmarking, simulation and application profiling. The Mess benc... » read more

Chip Industry Week In Review

By The SE Staff - 19 Apr, 2024 - Comments: 0

SK hynix and TSMC plan to collaborate on HBM4 development and next-generation packaging technology, with plans to mass produce HBM4 chips in 2026. The agreement is an early indicator for just how competitive, and potentially lucrative, the HBM market is becoming. SK hynix said the collaboration will enable breakthroughs in memory performance with increased density of the memory controller at t... » read more

Make The Impossible Possible: Use Variable-Shaped Beam Mask Writers And Curvilinear Full-Chip Inverse Lithography Technology For 193i Contacts/Vias With Mask-Wafer Co-Optimization

By eBeam Initiative - 22 Feb, 2024 - Comments: 0

Abstract: "Full-chip curvilinear inverse lithography technology (ILT) requires mask writers to write full reticle curvilinear mask patterns in a reasonable write time. We jointly study and present the benefits of a full-chip, curvilinear, stitchless ILT with mask-wafer co-optimization (MWCO) for variable-shaped beam (VSB) mask writers and validate its benefits on mask and wafer at Micron Tec... » read more

← Older posts

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

NAND Flash Targets 1,000 Layers

New techniques go beyond improved deposition and etching, but challenges stack up, too.

by Bryon Moyer

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

tag: Micron Technology

Chip Industry Week In Review

Chip Industry Week in Review

CXL’s Potential to Elevate The Capabilities of HPC and AI Applications (Micron, Intel)

Chip Industry Week In Review

Luminary Panel Sees Multi-Beam Mask Writers And Curvilinear Masks Key To 193i And EUV

Blog Review: Aug. 21

CD Spec For Curvilinear Masks

Memory System Benchmarking, Simulation, And Application Profiling Via A Memory Stress Framework

Chip Industry Week In Review

Make The Impossible Possible: Use Variable-Shaped Beam Mask Writers And Curvilinear Full-Chip Inverse Lithography Technology For 193i Contacts/Vias With Mask-Wafer Co-Optimization

Trending Articles

Baby Steps Toward 3D DRAM

What’s Next For Through-Silicon Vias