tag: Microsoft Research

Chip Industry Technical Paper Roundup: Feb. 10
By Linda Christensen - 10 Feb, 2025 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=405 /] Find all technical papers here. Also find more research and latest news here. » read more

Wafer-Scale Computing for LLMs (U. of Edinburgh, Microsoft)
By Technical Paper Link - 09 Feb, 2025 - Comments: 0

A new technical paper titled "WaferLLM: A Wafer-Scale LLM Inference System" was published by researchers at University of Edinburgh and Microsoft Research. Abstract "Emerging AI accelerators increasingly adopt wafer-scale manufacturing technologies, integrating hundreds of thousands of AI cores in a mesh-based architecture with large distributed on-chip memory (tens of GB in total) and ultr... » read more

New Class Of Memory: Managed-Retention Memory or MRM (Microsoft Research)
By Technical Paper Link - 22 Jan, 2025 - Comments: 0

A new technical paper titled "Managed-Retention Memory: A New Class of Memory for the AI Era" was published by researchers at Microsoft. Abstract "AI clusters today are one of the major uses of High Bandwidth Memory (HBM). However, HBM is suboptimal for AI workloads for several reasons. Analysis shows HBM is overprovisioned on write performance, but underprovisioned on density and read band... » read more

Chip Industry Technical Paper Roundup: Sept. 3
By Linda Christensen - 03 Sep, 2024 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=256 /] More ReadingTechnical Paper Library home » read more

Chip Industry Technical Paper Roundup: July 30
By Linda Christensen - 30 Jul, 2024 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library, including a best paper award winner at ISCA. [table id=246 /] More ReadingTechnical Paper Library home » read more

Co-optimizing HW Architecture, Memory Footprint, Device Placement And Per-Chip Operator Scheduling (Georgia Tech, Microsoft)
By Technical Paper Link - 28 Jul, 2024 - Comments: 0

A technical paper titled “Integrated Hardware Architecture and Device Placement Search” was published by researchers at Georgia Institute of Technology and Microsoft Research. Abstract: "Distributed execution of deep learning training involves a dynamic interplay between hardware accelerator architecture and device placement strategy. This is the first work to explore the co-optimization ... » read more

Power/Performance Bits: Mar. 11
By Jesse Allen - 11 Mar, 2019 - Comments: 0

Reading qubits faster Researchers at Aalto University and VTT Technical Research Centre of Finland propose a faster way to read information from qubits, the building blocks of quantum computers. Currently, they are extremely sensitive to disruption even in cryogenic environments, holding quantum information for less than a millisecond. In the method now used to read information from a qubit... » read more

The Week in Review: IoT
By Jeff Dorsch - 08 Dec, 2017 - Comments: 0

Products/Services Vancouver, B.C.-based Riot Micro has brought out the RM1000 baseband modem chip for the cellular Internet of Things. The device is said to use Bluetooth Low Energy and Wi-Fi techniques to provide low-power and lower-cost connectivity, like short-range wireless systems. The chip is being marketed to module manufacturers and OEMs developing narrowband IoT and LTE-M products for... » read more

System Bits: Aug. 30
By Ann Mutschler - 30 Aug, 2016 - Comments: 0

Probing photon-electron interactions According to Rice University researchers, where light and matter intersect, the world illuminates; where they interact so strongly that they become one, they illuminate a world of new physics. Here, the team is closing in on a way to create a new condensed matter state in which all the electrons in a material act as one by manipulating them with light and a... » read more

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