tag: Mobiveil

Move Data Or Process In Place? (Part 2)
By Brian Bailey - 20 Nov, 2017 - Comments: 0

Chip architectures, and even local system architectures, long have found that the best way to improve total system performance and power consumption is to move memory as close to processors as possible. This has led to cache architectures and memories that are tuned for those architectures, as discussed in part 1 of this article. But there are several tacit assumptions made in these architectur... » read more

New Drivers For I/O
By Brian Bailey - 13 Nov, 2017 - Comments: 0

Interface standards are on a tear, and new markets are pushing the standards in several directions at the same time. The result could be a lot more innovation and some updates in areas that looked to be well established. Traditionally, this has been a sleepy and predictable part of the industry with standards bodies producing updates to their interfaces at a reasonable rate. Getting data int... » read more

The Week In Review: Design
By Jesse Allen - 13 Oct, 2017 - Comments: 0

Storage Western Digital uncorked disk drives based upon microwave-assisted magnetic recording technology. MAMR technology is one of two energy-assisted technologies the company has under development, the other being heat-assisted magnetic recording. Of the two, Western Digital said only MAMR has achieved the reliability required in data centers. The company noted that densities of its MAMR dev... » read more

Trimming Waste In Chips
By Brian Bailey - 12 Oct, 2017 - Comments: 0

Extra circuitry costs money, reduces performance and increases power consumption. But how much can really be trimmed? When people are asked that question they either get defensive or they see it as an opportunity to show the advantages of their architecture, design process or IP. The same holds true for IP suppliers. Others point out that the whole concept of waste is somewhat strange, becau... » read more

The Week In Review: Design
By Jesse Allen - 15 Sep, 2017 - Comments: 0

Tools Cadence unveiled a new equivalence checking tool which features a massively parallel architecture capable of scaling to 100s of CPUs and adaptive proof technology that analyzes each partition and determines the optimal formal algorithm. According to the company, the Conformal Smart Logic Equivalence Checker provides an average of 4X runtime improvement with the same resources over the pr... » read more

Is Design Innovation Slowing?
By Brian Bailey - 10 Aug, 2017 - Comments: 0

Paul Teich, principal analyst for Tirias Research, gave a provocative talk at the recent DAC conference entitled, "Is Integration Leaving Less Room for Design Innovation?" The answer isn't as simple as the question might suggest. "Integration used to be a driver for increasing the functionality of silicon," Teich said. "Increasingly, it will be used to incorporate more features of an entire ... » read more

The Week In Review: Design
By Jesse Allen - 04 Aug, 2017 - Comments: 0

M&A Invecas will acquire Lattice Semiconductor's HDMI design team and Simplay Labs subsidiary, which oversees standards compliance and interoperability testing services. Invecas supplies foundation, analog, and interface IP optimized for GlobalFoundries processes. The deal is expected to close later this month. Last year, Lattice announced it would be acquired by Chinese private equity fir... » read more

Transient Power Problems Rising
By Ann Mutschler - 08 Jun, 2017 - Comments: 0

Transient power is becoming much more problematic at 10/7nm, adding yet another level of complexity for design teams already wrestling with power issues caused by leakage, a variety of power management techniques to control dynamic power, and leakage current. At each new node there is less headroom for engineering teams to address these problems, and more likelihood that what they do in one ... » read more

RISC-V Pros And Cons
By Ann Mutschler - 29 May, 2017 - Comments: 7

Simpler, faster, lower-power hardware with a free, open, simple instruction set architecture? While it sounds too good to be true, efforts are underway to do just that with RISC-V, the instruction-set architecture (ISA) developed by UC Berkeley engineers and now administered by a foundation. It has been known for some time that with [getkc id="74" comment="Moore's Law"] not offering the same... » read more

The Week In Review: Design
By Jesse Allen - 28 Apr, 2017 - Comments: 0

IP ARM launched the Mali-C71 image signal processor (ISP), targeting ADAS SoCs. The ISP is capable of processing up to 4 real-time cameras and 16 camera streams with a single pipeline and provides advanced error detection with more than 300 dedicated fault detection circuits. Included is full reference software to control the ISP, sensor, auto white balance and auto exposure. Synopsys ext... » read more

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