The Week In Review: Design

IP

ARM launched the Mali-C71 image signal processor (ISP), targeting ADAS SoCs. The ISP is capable of processing up to 4 real-time cameras and 16 camera streams with a single pipeline and provides advanced error detection with more than 300 dedicated fault detection circuits. Included is full reference software to control the ISP, sensor, auto white balance and auto exposure.

Synopsys extended its portfolio of ASIL B and D Ready ISO 26262 certified IP to include PCI Express 3.1 controller and PHY, USB 3.0 controller, MIPI CSI-2 controllers and D-PHY, LPDDR4 PHY, EEPROM and Trim NVM. The IP was certified by SGS-TÜV Saar.

CAST and Beyond Semiconductor unveiled an IP core that builds secure code execution into a 32-bit processor suitable for embedded systems and IoT devices. The Geon core uses two or more cryptographically separated execution contexts for security during code execution and for data storage and transfer to and from the processor. The 32-bit processing unit uses a five-stage pipeline and achieves up to 1.79 DMIPs/MHz.

Inside Secure released the latest version of its true random number generator IP, which the company says is 50 times more efficient than what’s on the market today. The IP uses a Shot Noise oscillator implementation allowing operation across very wide PVT ranges as encountered in 45nm and below semiconductors.

Mobiveil’s Flash Reliability IP is now available for use in the eASIC Nextreme-3S family. The Flash Reliability IP Platform contains an LDPC (Low Density Parity Check) engine with a Flash Interface, Flash Soft-Information Generation and Flash Monitoring and Analysis. The LDPC engine is programmable to support any codeword/parity combination from 512B to over 8KB and supports on-the-fly switching between different LDPC codes.

Tools

Imperas joined the RISC-V Foundation and added virtual platform and model support for the RISC-V architecture to aid in building and customization of instruction accurate models and platforms for software development.

Imagination uncorked a development environment for its MIPS M-class and I-class CPU IP cores. The package includes Codescape Debugger and Codescape for Eclipse IDE, Bus Blaster JTAG debug probes, and a complete GCC toolchain. It is priced at approximately $45 per development seat.

Deals

Wave Computing selected Synopsys‘ emulation solution for early software bring-up and development for its Dataflow Processing Unit (DPU) architecture. According to Wave, this accelerated the development of its machine learning software by 12 months. Wave also used Sonics‘ Interleaved Multichannel Technology (IMT) to enable the connection of both Hybrid Memory Cube (HMC) and DDR memories by a single NoC fabric.

Amlogic adopted Cadence’s FPGA-Based Prototyping Platform for developing multimedia SoCs. Amlogic cited the ability to run multiple instances of the design in parallel and accelerated time to prototype.

Starblaze used Synopsys‘ DesignWare Security and Foundation IP for its STAR1000 enterprise SSD SoC, including the use of True Random Number Generators to meet new security requirements for the China market and memory test and repair to reduce SoC area by 7%.

Standards

The MIPI Alliance hosted the first plugfest for the MIPI I3C sensor interface specification, giving early adopters an opportunity to perform interoperability testing of their designs for smartphones, IoT, automotive and other applications.

Numbers

Cadence released first quarter 2017 financial results with revenue of $477 million, up 6.5% from the first quarter last year. On a GAAP basis, the company saw income of $0.25 per share, up 47% from $0.17 in Q1 2016. Non-GAAP income per share was $0.32 in Q1 2017, up 14.3% from $0.28 in the first quarter 2016.

Rambus reported first quarter financial results with revenue of $97.4 million, up 34% from the first quarter of 2016. On a GAAP basis, income per share for Q1 2017 was $0.03, up 50% from $0.02 in Q1 2016. Non-GAAP income for the quarter was $0.17 per share, up 30.8% from $0.13.