The Week In Review: Design

Microwave-assisted storage; photonic design; functional safety; time-sensitive networking; Gartner’s chip forecast.


Western Digital uncorked disk drives based upon microwave-assisted magnetic recording technology. MAMR technology is one of two energy-assisted technologies the company has under development, the other being heat-assisted magnetic recording. Of the two, Western Digital said only MAMR has achieved the reliability required in data centers. The company noted that densities of its MAMR devices are expected to reach 4 TB per square inch, so that by 2025 hard drives will have capacities of up to 40 TB. MAMR uses spin torque oscillators to generate microwave fields inside of sealed helium-filled units. That, in turn, allows ultra-high density at high reliability, according to WD.

Synopsys released the latest version of its photonic component and optical communication system design suites. Additions include the S-Matrix/PDK Generation Utility for multi-level photonic integrated circuit design and analysis, expanded EIM implementation for reducing 3D waveguide structures for simulation, and an interface with Synopsys’ HSPICE circuit simulation tool.

Cadence flows and documentation gained TÜV SÜD’s “Fit for Purpose – Tool Confidence Level 1 (TCL1)” certification. The certification states Cadence flows are fit for use with ISO 26262 ASIL A through ASIL D automotive design projects and provides functional safety documentation kits.

Cadence announced that its digital and signoff flow supports body-bias interpolation for GlobalFoundries’ 22FDX process technology.

Rambus released a suite of SerDes solutions developed for GlobalFoundries’ FX-14 ASIC platformm including 16G MPSL (multi-protocol serial link), 30G C2C (chip-to-chip) and 30G VSR (very short reach) PHYs. The PHYs are optimized for power and area at peak bandwidth.

Mobiveil launched digital controller IP compliant with the 25xN RapidIO Specification 4.1 fabric architecture. The latest specification offers 100 Gbps per port with support for high-availability and safety-critical extensions. The IP is currently available for the ASIC market, with an FPGA version available next year.

SoC-e uncorked a multiport Time Sensitive Networking (TSN) IP core. Designed to be implemented on Xilinx Zynq-7000 and Zynq Ultrascale+ MPSoC, the IP supports IEEE 802.1AS for time synchronization of the network nodes to a reference time and  IEEE 802.1Qbv for enhanced traffic scheduling.

Sandia National Laboratories licensed Flex Logix’s EFLX reconfigurable logic IP.  The logic core will be implemented in Sandia’s proprietary 180nm process for the development of multiple Sandia chip products for use in Sandia projects.

Teradyne adopted Cadence’s Xcelium Parallel Logic Simulator for ASIC development for delivery of automation equipment for test and industrial applications. Teradyne cited a 2X performance speedup when compared with its previous simulation solution.

Efinix will use Verific’s parser platform and RTL elaborator to serve as the front end to its Efinity Integrated Design Environment (IDE), which will support the company’s programmable products for deep learning and compute acceleration applications.

ArterisIP joined GlobalFoundries’ FDXcelerator Partner Program, enabling its interconnect IP, cache coherent interconnect IP, and timing closure package for FDX-based designs.

Market research firm Gartner predicts worldwide semiconductor revenue will total $411.1 billion in 2017, an increase of 19.7% from 2016. Memory continues to drive the market higher and is expected to increase 57%. Meanwhile, nonoptical sensors, analog, discretes and image sensors are forecast to grow over 10%. Further out, Gartner sees a 4% increase in 2018 before a 1% fall in 2019.

DVCon Europe: Oct. 16-17 in Munich, Germany. The annual conference for design and verification features keynotes by Bosch’s Horst Symanzik on the design challenges of consumer MEMS products, plus a discussion of virtual prototyping of automotive electronics by Audi’s Berthold Hellenthal.

Arm TechCon: Oct. 24-26 in Santa Clara, CA. The Arm ecosystem-focused conference features a number of keynotes from Arm on subjects from the value of IoT data to state-of-the-art silicon process technologies. Invited speakers Stacey Higginbotham, Mary Aiken, and Jessica Barker will discuss the key challenges facing IoT and why a more human-centered approach is needed when designing security.

The public review period for the Portable Stimulus Specification has been extended to Oct. 30. The specification defines a standard mechanism for the specification of verification intent and behaviors that would be reusable across target platforms and allow for the automation of test generation through a new Domain Specific language and equivalent C++ Class Library. The Early Adopter release is available from Accellera.