Who’s Profiting From Complexity


Tool vendors' profits increasingly are coming from segments that performed relatively poorly in the past, reflecting both a rise in complexity in designing chips and big improvements in the tools themselves. The impacts of power, memory congestion, advanced-node effects such as process variation, [getkc id="160" kc_name="electromigration"] and RC delay in [getkc id="36" kc_name="interconnect... » read more

How To Model Cars


The most technologically advanced and comprehensive consumer product in the world today is not the smartphone. It's the automobile. This is easier to see once the hood is up and you can take a peek around. Today’s cars contain sophisticated motion systems, crash safety systems, climate control systems, driver assistance, and infotainment, to name a few. In semiconductor design, one of the ... » read more

Outbound Power Management


Many years ago when I first suggested that we should do platform-level power instead of focusing on the CPU, I was considered somewhat of a heretic. Yet, within 10 to 15 years of that recommendation, most of the platforms around us have moved to that method using operating system functions to keep track of the overall power, battery life, etc. As we move into the era of billions of connected de... » read more

IP Integration Challenges Increase


Semiconductor Engineering sat down with Chris Rowen, CTO of [getentity id="22032" e_name="Cadence"]'s IP group; Rob Aitken, an [getentity id="22186" comment="ARM"] fellow; Patrick Soheili, vice president of product management and corporate development at [getentity id="22242" e_name="eSilicon"]; Navraj Nandra, senior director of marketing for DesignWare analog and mixed-signal IP at [getentity ... » read more

What Is Functional Accuracy?


What it means to be functionally accurate in the context of [getkc id="104" kc_name="virtual platforms"] varies greatly, depending upon whom you ask and even when you ask them. But that doesn’t mean that functional accuracy isn’t useful. Jon McDonald, technical marketing engineer for the design and creation business at [getentity id="22017" e_name="Mentor Graphics"], expects to see a lot... » read more

How Many Levels Of Abstraction Are Needed?


Recently I was having a conversation with a user who was creating cycle accurate SystemC models. My initial thought was, "Why would this be necessary?" Through the course of discussions I realized that he did have a design questions that required that level of accuracy and the simulation performance trade-offs were appropriate for his needs. His cycle accurate SystemC models were running at abo... » read more

Are Models Holding Back New Methodologies


Semiconductor Engineering sat down to discuss the state of the industry for [getkc id="101" kc_name="modeling"] at abstractions above [getkc id="49" kc_name="RTL"], a factor which has delayed adoption of [getkc id="104" kn_name="virtual prototypes"] and the proliferation of system-level design and hardware/software codesign. Taking part in the discussion were Frank Schirmeister, group director,... » read more

Not Invented Here Syndrome


Recently I have made some choices on IP I needed to re-use and some I decided not to re-use. This got me thinking about the general topic of reuse in system-level design. Most will agree with a non-specific statement that reuse is a good thing, but the details tend to be a bit more ambiguous. Clouding the reuse question are occasional infections of NIH Syndrome (Not Invented Here), even if s... » read more

High-Level Gaps Emerge


Semiconductor Engineering sat down to discuss the attributes of a high-level, front-end design flow, and why it is needed at present with Leah Clark, associate technical director for digital video technology at Broadcom; Jon McDonald, technical marketing engineer at Mentor Graphics; Phil Bishop, vice president of the System Level Design System & Verification Group at Cadence; and Bernard Mu... » read more

The Week In Review: Design


Tools Mentor Graphics rolled out embedded Linux software for AMD’s x86 G-series SoCs, code-named Steppe Eagle and its Crowned Eagle CPUs. Ansys-Apache and TowerJazz have created a power noise and reliability signoff design kit, including reference flow guidelines, test case examples and flow setup guidance. Synopsys updated its verification portfolio with static and formal tools for CD... » read more

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