Why Packaging Matters

By Ed Sperling - 19 Nov, 2015 - Comments: 1

The semiconductor package is changing. What was until very recently considered an afterthought is now becoming a key part of the design process at all major chipmakers, and a critical factor in the extension of Moore's Law. This is a sharp reversal of what was almost universally an afterthought in planar silicon design and manufacturing. Rarely was the package an integral part of the archite... » read more

Is HW Or SW Running the Show?

By Brian Bailey - 24 Sep, 2015 - Comments: 1

In the past, hardware was designed and then passed over to the software team for them to add their contribution to the product. This worked when the amount of software content was small and the practice did not significantly contribute to product delays. Over time, the software content grew and today it is generally accepted that software accounts for more product expense than hardware, takes l... » read more

Electronics Butterfly Effect

By Brian Bailey - 27 Aug, 2015 - Comments: 1

Everyone has heard of the butterfly effect where a small change in a non-linear system can result in large difference in an outcome. For the past 40 years, the electronics industry has approximated a linear system, fed primarily by Moore’s Law. The incremental changes available at each new process node have led us to make incremental changes and improvements in many aspects of the design, its... » read more

Manufacturing And Packaging Changes For 2015

By Brian Bailey - 22 Jan, 2015 - Comments: 0

This year more than 26 people provided predictions for 2015. Most of these came from the EDA industry, so the results may be rather biased. However, ecosystems are coming closer together in many parts of the semiconductor food chain, meaning that the EDA companies often can see what is happening in dependent industries and in the system design houses. Thus their predictions may have already res... » read more

One-On-One: Aaron Thean

By Mark LaPedus - 22 Jan, 2015 - Comments: 0

Semiconductor Engineering sat down to discuss process technology, transistor trends and other topics with Aaron Thean, vice president of process technologies and director of the logic devices R&D program at Imec. SE: Chipmakers are ramping up the 16nm/14nm logic node, with 10nm and 7nm in R&D. What’s the current timeline for 10nm and 7nm? Thean: 10nm is on its way. We will see r... » read more

Signal And Power Integrity Cross Paths

By Ed Sperling - 05 Dec, 2014 - Comments: 2

Signal integrity and power integrity historically have been relatively independent issues, and engineers with expertise in one area generally operate independently of the other. But as more power domains are added to conserve energy and allow more features, as voltages are reduced to save battery life, and as dynamic power becomes more of a concern at advanced nodes, these worlds are suddenly m... » read more

Transistor Options Narrow For 7nm

By Mark LaPedus - 13 Nov, 2014 - Comments: 0

Chipmakers are currently ramping up silicon-based finFETs at the 16nm/14nm node, with plans to scale the same technology to 10nm. Now, the industry is focusing on the transistor options for 7nm and beyond. At one time, the leading contenders involved several next-generation transistor types. At present, the industry is narrowing down the options and one technology is taking a surprising lea... » read more

Will 7nm And 5nm Really Happen?

By Mark LaPedus - 14 Jul, 2014 - Comments: 2

Today’s silicon-based finFETs could run out of steam at 10nm. If or when chipmakers move beyond 10nm, IC vendors will require a new transistor architecture. III-V finFETs, gate-all-around FETs, quantum well finFETs, SOI finFETs and vertical nanowires are just a few of the future transistor candidates at 7nm and 5nm. Technically, it’s possible to manufacture the transistor portions of the... » read more

What Comes Next?

By SEMI - 27 Jun, 2014 - Comments: 0

The latest manufacturing, materials and production developments for emerging and adjacent markets will be featured at SEMICON West 2014 (www.semiconwest.org), to be held on July 8-10 at the Moscone Center in San Francisco, Calif. The co-location of emerging and adjacent market focused exhibitors and technical presentations within the framework of SEMICON West maximizes the synergies between sem... » read more

3D Integration

By Katherine Derbyshire - 23 Apr, 2013 - Comments: 0

By Katherine Derbyshire It’s a central problem of integrated circuit scaling. While transistor delay goes down along with channel length, interconnect delay goes up. The 90 nm technology node featured a transistor delay of about 1.6 ps, while a 1 mm long interconnect wire added about 5x102 ps. For the 22 nm node, the ITRS estimates transistor delay at 0.4 ps, but interconnect delay at abou... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?