Transistor Options Narrow For 7nm

The frontrunner is sill a silicon-based finFET, but there are lots of other options on the table.

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Chipmakers are currently ramping up silicon-based finFETs at the 16nm/14nm node, with plans to scale the same technology to 10nm. Now, the industry is focusing on the transistor options for 7nm and beyond.

At one time, the leading contenders involved several next-generation transistor types. At present, the industry is narrowing down the options and one technology is taking a surprising lead in the 7nm transistor race—today’s silicon-based finFET. This technology could go in two directions, namely 7nm bulk CMOS finFETs or SOI finFETs. And in both cases, a 7nm finFET could introduce germanium into the channel.

This, of course, could change overnight if the semiconductor industry finds a better transistor option. Some chipmakers, namely Intel, may even leapfrog the competition and move to a next-generation transistor at 7nm. The leading contender is the gate-all-around FET. Other options include III-V finFETs, nanowire FETs and quantum well finFETs.

But for now, the risk-adverse IC industry would prefer to extend a known quantity like finFETs for at least two more generations. It allows IC designers to leverage the existing finFET infrastructure. And at 7nm, it might be too risky and expensive to go with a next-generation transistor. “We can scale the finFET to 7nm kind of dimensions,” said Terry Hook, senior technical staff member at IBM. “We prefer to scale. You don’t want a disruption (in terms of moving to a new architecture). From an engineering perspective, it’s less exciting. But you don’t want to live in exciting times, so to speak.”

But scaling the finFET to 7nm presents some major challenges. Moving to a next-generation transistor is also not a simple task. And for now, it’s too early to tell which technology will prevail at 5nm and beyond.

The safest path
In the previous roadmaps among many entities, today’s silicon-based finFETs were supposed to hit the wall at 10nm. Then, at 7nm, the leading transistor candidate was the high-mobility or III-V finFET, followed by a next-generation transistor type at 5nm.

But as it stands right now, today’s finFETs can scale much further than previously thought. III-V materials are not ready for 7nm. And the industry continues to work on the next-generation transistor types for 5nm and possibly at 7nm.

Still, there are many unknowns, so chipmakers are keeping their options open. For now, though, the safest path is to scale today’s finFETs to 7nm. “Based on what I’ve seen, people will try and scale finFETs to avoid having to change the type of transistor,” said Chris Hobbs, process, materials and ESH program manager at Sematech. “People are looking at a lot of different things at the 10nm and 7nm node. People are doing finFETs now. I would expect finFETs at those nodes too.”

In today’s finFETs, the control of the current is accomplished by implementing a gate on each of the three sides of a fin. In theory, a 7nm finFET would include traditional transistor features, such as copper interconnects, low-k and a high-k/metal-gate stack. The fin height remains a moving target, but the fin width could measure around 5nm. In comparison, the fin width for Intel’s finFET technology is 13nm at the 22nm node and 8nm at the 14nm node, according to estimates.

From there, a 7nm finFET could go in different directions. For example, chipmakers could go with either bulk finFETs or SOI finFETs using fully depleted silicon-on-insulator (FDSOI) technology. Both have some advantages and disadvantages. On one hand, SOI substrates are more expensive than bulk wafers. But on the other hand, SOI finFETs are supposedly easier to make. “(FDSOI) enables better gate height control,” IBM’s Hook said. For years, IBM has been a proponent of FDSOI.

Perhaps the biggest difference between today’s finFETs and 7nm finFETs are the channel materials. For 10nm and/or 7nm, chipmakers may introduce germanium in the channel, which is expected to boost the overall mobilities in the device. Chipmakers also are looking at the more exotic III-V materials for 7nm, but the industry may push out those compounds until 5nm. With III-V materials, chipmakers must contend with lattice mismatches and other issues.

“[The idea is to] change the material to something other than silicon, which intrinsically has a higher electron and hole mobility. That’s the focus of our industry right now for the next node, maybe 10nm or 7nm.” said Reza Arghavani, a fellow at Lam Research. “So around 10nm, you may see silicon slowly moving towards germanium (in the channel). Regarding III-V, that’s more of a challenging transition. But it’s not an impossible transition.”

Making a 7nm finFET is easier said than done. There are a multitude of difficult and expensive process steps. One of the more daunting challenges is to make the fin structure. The first step is patterning. For the fin patterning step alone, the industry is looking at four different Lithography options at 7nm—193nm immersion and self-aligned quadruple patterning; 193nm and directed self-assembly (DSA); extreme ultraviolet (EUV) lithography and self-aligned double patterning; or EUV and DSA.

Chipmakers want to insert EUV to simplify the patterning steps at 7nm. But according to a recent survey from the eBeam Initiative, it’s unclear if EUV will be ready by then. “The survey echoes the statements from many in the industry: ‘We still want (EUV) to happen.’ But publicly, everyone is saying: ‘I don’t know if we can count on it. So we better have backup plans in place,’ “ said Aki Fujimura, chairman and chief executive of D2S.

After the patterning flow is determined, chipmakers can then consider the next difficult step—making the finFET with germanium in the channel. For this step, there are two different options—direct etch or fin replacement. “With direct etch, you basically grow germanium or silicon germanium on a large area. And then, you use lithography to pattern the fin, much as you would with a silicon fin,” Sematech’s Hobbs said. “(In replacement fin), you would form a dummy of silicon in the STI process. Then, you would do some type of a process to etch back the fin. And then, you would re-grow germanium or silicon germanium in the place where the dummy fin was.”

Now, here comes the hard part. First, chipmakers must decide whether the germanium mix should be for PFET and/or NFET. The first devices will likely include germanium for PFET. The NFET may come later. Then, vendors must decide how much germanium content should go into PFET and/or NFET.

“The industry is still looking at how much germanium you need. Our data has shown a very nice boost on a PFET with 25% germanium. Some of the lower percentages could work for a PFET,” Hobbs said. “A higher percentage would help boost it even further. People may want to adopt a lower percentage early on and switch to a higher percentage later. That will be a choice for the individual companies. It’s an optimization process.”

The industry faces some challenges when moving from silicon to germanium in the channel. “High mobility comes with a lower bandgap,” said Adam Brand, senior director of the transistor technology group at Applied Materials. “Germanium has some issues to overcome. The bandgap is very low. What that means is that there is a lot of leakage in this material.”

To simplify matters, the industry could integrate germanium for PFET, while maintaining the existing silicon content for NFET. “Silicon is still a nice material for NMOS. But even if silicon stays in place on the channel for the NMOS device, there is still a lot of device formation complexity. For example, these device structures may require complicated epi layer stacks,” Brand said.

Next-gen transistors

There are also a plethora of other challenges to make finFETs at 7nm. The challenges are fueling another school of thought—move to a next-generation transistor type at 7nm and/or 5nm. Based on the current calculations, today’s finFET could run out of gas at 5nm, prompting the need for a new technology. “Right now, the numbers are problematic near 5nm,” Lam’s Arghavani said. “We are putting a (transistor technology) change somewhere between 7nm to 5nm, possibly around 5nm.”

To date, there is no consensus in the next-generation transistor arena, as each technology has its pluses and minuses. One option—the III-V finFET—is a finFET with III-V materials in the channels. Meanwhile, in gate-all-around, a gate is placed on all four sides of the channel. The stacked nanowire FET is an offshoot of gate-all-around. Then, there are the more exotic technologies like tunnel FETs (TFETs) and monolithic 3D chips.

The most appealing option, according to Applied’s Brand, is gate-all-around. “Density is the imperative that’s going to drive things forward. So gate-all-around is the way we are going to address that. TFETs aren’t going to address density. In many ways, it will make it worse. There is even a question whether III-V can actually address the density challenges,” Brand said.

Other options include the 3D-based technologies. IMEC, for one, is developing a vertical nanowire device. “There is active research in devices like gate-all-around stacked nanowire devices that evolve from the finFET architecture,” said Aaron Thean, director of the logic program at Imec. “These devices provide more short-channel electrostatic control, but they also add much higher process complexity, especially when stacked tall and dense.”

Meanwhile, CEA-Leti is developing monolithic 3D chips. This involves a process of stacking leading-edge transistors to form a monolithic 3D chip. “There is a major fundamental physical problem (with monolithic 3D),” Applied’s Brand said. “You have a much more restrictive thermal budget for anneals, deposition and epi. Annealing is the most challenging problem.”

Then, there is the old standby—the finFET. The III-V finFET could be a viable option at 5nm. It could even push out the need for a next-generation transistor at 5nm. “It’s more likely for people to continue with a finFET type of structure on III-V than to switch the architecture at that point,” Sematech’s Hobbs said.

Still, it’s too early to make a prediction for 5nm. Beyond 5nm, the industry is looking at a number of post-CMOS technologies, all of which remain challenging. “Technologies like carbon nanotubes are not coming into prime time soon,” Applied’s Brand said. “Silicon will go pretty far.”