Week In Review: Semiconductor Manufacturing, Test

By Karen Heyman - 28 Apr, 2023 - Comments: 0

The U.S. Commerce Department launched Chips.gov, a website that covers all aspects of the CHIPS Act, including funding opportunities and job openings. In similar vein, Intel CEO Pat Gelsinger focused on the future of semiconductor manufacturing in America in a talk at MIT. Intel has committed to expanding semiconductor manufacturing in the U.S., including spending an initial $20 billion on ne... » read more

Improving the Electrical Performance and Low-Frequency Noise Properties of p-Type TFET

By Technical Paper Link - 08 Nov, 2022 - Comments: 0

A new technical paper titled "Effect of high-pressure D2 and H2 annealing on LFN properties in FD-SOI pTFET" was published by researchers at Chungnam National University and Korea Polytechnic College. "This study investigated the effects of high-pressure deuterium (D2) annealing and hydrogen (H2) annealing on the electrical performance and low-frequency noise (LFN) of a fully depleted silic... » read more

Inside Next-Gen Transistors

By Mark LaPedus - 20 Apr, 2017 - Comments: 0

David Fried, chief technology officer at [getentity id="22210" e_name="Coventor"], sat down with Semiconductor Engineering to discuss the IC industry, China, scaling, transistors and process technology. What follows are excerpts of that conversation. SE: In a recent roundtable discussion you talked about some of the big challenges facing the IC industry. One of your big concerns involves th... » read more

TFETs And/Or MOSFETs For Low-Power Design

By Katherine Derbyshire - 16 Mar, 2017 - Comments: 0

As discussed in Reducing Subthreshold Swing With TFETs, papers at December’s IEEE Electron Device Meeting examined a variety of potential designs for tunneling transistors (TFETs). That focus continued at the recent CS International Conference. In particular, Nadine Collaert discussed IMEC’s work on InGaAs homo-junction devices. Many compound semiconductor devices depend on heterojunctio... » read more

Pathfinding Beyond FinFETs

By Paula Doe - 13 Jun, 2016 - Comments: 0

Though the industry will likely continue to find ways to extend CMOS finFET technology further than we thought possible, at some point in the not-so-distant future, making faster, lower power ICs will require more disruptive changes. For something that could be only five to seven years out, there’s a daunting range of contending technologies. Improvements through the process will help, from E... » read more

Power/Performance Bits: Dec. 8

By Jesse Allen - 08 Dec, 2015 - Comments: 0

Reducing transistor switching power One of the great challenges in electronics has been to reduce power consumption during transistor switching operation. However, engineers at University of California, Santa Barbara, and Rice University demonstrated a new transistor that switches at only 0.1 volts and reduces power dissipation by over 90% compared to state-of-the-art MOSFETs. "The steepn... » read more

Raise A Fence, Dig A Tunnel, Build A Bridge

By Ed Sperling - 17 Sep, 2015 - Comments: 0

There are three main options for chipmakers over the course of the next decade. Which option they choose depends upon their individual needs, talents, and how much and what kind of differentiation they believe will matter to them. The options roughly fall into three categories—fence, bridge or tunnel. The fence option Rather than changing anything, the entire ecosystem can stick to wha... » read more

What’s After 10nm?

By Ed Sperling - 21 May, 2015 - Comments: 0

Prior to 28nm the semiconductor road map was astoundingly predictable. Every two years you could be assured that features would shrink until there were no more atoms left. Two big things and lots of little things later, the trajectory looks much more uncertain. On the large things side are the obvious culprits—EUV delays, and RC delay caused by thinner wires. This is tough science. Pro... » read more

One-On-One: Aaron Thean

By Mark LaPedus - 22 Jan, 2015 - Comments: 0

Semiconductor Engineering sat down to discuss process technology, transistor trends and other topics with Aaron Thean, vice president of process technologies and director of the logic devices R&D program at Imec. SE: Chipmakers are ramping up the 16nm/14nm logic node, with 10nm and 7nm in R&D. What’s the current timeline for 10nm and 7nm? Thean: 10nm is on its way. We will see r... » read more

Transistor Options Narrow For 7nm

By Mark LaPedus - 13 Nov, 2014 - Comments: 0

Chipmakers are currently ramping up silicon-based finFETs at the 16nm/14nm node, with plans to scale the same technology to 10nm. Now, the industry is focusing on the transistor options for 7nm and beyond. At one time, the leading contenders involved several next-generation transistor types. At present, the industry is narrowing down the options and one technology is taking a surprising lea... » read more

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Knowledge Centers
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tag: TFETs