New Tradeoffs In Leading-Edge Chip Design

By Katherine Derbyshire - 21 Nov, 2024 - Comments: 0

Device design begins with the anticipated workload. What is it actually supposed to do? What resources — computational units, memory, sensors — are available? Answering these questions and developing the functional architecture are the first steps in a new design — well before committing it to silicon, said Tim Kogel, senior director of technical product management at Synopsys. Yet eve... » read more

Fine-Grained Functional Partitioning For Low Level SRAM Cache in 3D-IC designs (imec)

By Technical Paper Link - 27 Sep, 2024 - Comments: 0

A new technical paper titled "Towards Fine-grained Partitioning of Low-level SRAM Caches for Emerging 3D-IC Designs" was published by researchers at imec. "We propose a partitioning of low-level (faster access) caches in 3D using an Array Under CMOS (AuC) technology paradigm. Our study focuses on partitioning and optimization of SRAM bit-cells and peripheral circuits, enabling heterogeneous ... » read more

Wafer-Scale CMOS-Integrated GFET Arrays With High Yield And Uniformity Designed For Biosensing Applications

By Technical Paper Link - 06 Sep, 2023 - Comments: 0

A technical paper titled “Wafer-Scale Graphene Field-Effect Transistor Biosensor Arrays with Monolithic CMOS Readout” was published by researchers at VTT Technical Research Centre of Finland and Graphenea Semiconductor SLU. Abstract: "The reliability of analysis is becoming increasingly important as point-of-care diagnostics are transitioning from single-analyte detection toward multiplex... » read more

III–V Laser Grown on a Patterned Si Photonics Platform With Light Coupling Into Passive SiN Waveguides

By Technical Paper Link - 28 Jul, 2023 - Comments: 0

A technical paper titled “Unlocking the monolithic integration scenario: optical coupling between GaSb diode lasers epitaxially grown on patterned Si substrates and passive SiN waveguides” was published by researchers at University of Montpellier, Tyndall National Institute, Munster Technological University and Polytechnic University of Bari. Abstract: "Silicon (Si) photonics has recently... » read more

Crystal Phase Control during Epitaxial Hybridization of III-V Semiconductors with Silicon

By Technical Paper Link - 21 Dec, 2021 - Comments: 0

Abstract: "The formation and propagation of anti-phase boundaries (APBs) in the epitaxial growth of III-V semiconductors on Silicon is still the subject of great debate, despite the impressive number of studies focusing on this topic in the last past decades. The control of the layer phase is of major importance for the future realization of photonic integrated circuits that include efficien... » read more

The Chip Industry’s Next-Gen Roadmap

By Mark LaPedus - 21 Jan, 2021 - Comments: 1

Todd Younkin, the new president and chief executive of the Semiconductor Research Corp. (SRC), sat down with Semiconductor Engineering to talk about engineering careers, R&D trends and what’s ahead for chip technologies over the next decade. What follows are excerpts of that conversation. SE: As a U.S.-based chip consortium, what is SRC's charter? Younkin: The Semiconductor Research... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

NAND Flash Targets 1,000 Layers

New techniques go beyond improved deposition and etching, but challenges stack up, too.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.