tag: Moore’s Law

Moore’s Law Revisited
By Ed Sperling - 31 Mar, 2011 - Comments: 0

By Ed Sperling The push to 20nm and beyond is creating some interesting gyrations in the EDA industry. While tools vendors continue to work on tools for the latest process nodes, they’re also taking some significant sidesteps. The first to publicly recognize a shift is under way was Cadence, which last year issued its EDA 360 manifesto. The strategy is to continue investing in existing to... » read more

Moore’s Law Will Never End
By Ed Sperling - 17 Dec, 2010 - Comments: 0

Moore’s Law has been many things to many people. It has been a statement of physical limits and an economic formula. It has been the cause of overheating and complex power solutions, and it has been a competitive weapon among companies looking to boost performance and cut costs. It also has been revised on more than one occasion as the time frame in which the number of transistors doubles ... » read more

Troubles At 15nm
By Ed Sperling - 16 Dec, 2010 - Comments: 0

For the better part of the past decade the most advanced companies and the big foundries were targeting 22nm as the bogeyman of chip development. Now it appears the big problems will crop up at 15nm. That means two things. First, the problems that were expected to crop up at 22nm—leakage, electromigration, electrostatic discharge, layout and even verification—appear to have been pushed o... » read more

The Growing Legacy Of Moore’s Law
By Ed Sperling - 02 Dec, 2010 - Comments: 0

By Ed Sperling Moore’s Law has defined semiconductor design since it was introduced in 1965, but increasingly it also has begun defining the manufacturing equipment, the cooling needed for end devices, and both the heat and performance of systems. In the equipment sector the big problem has been the delay in rolling out extreme ultraviolet (EUV). Moore’s Law will require tighter spacing... » read more

Getting Ready For 15nm
By Ed Sperling - 07 Oct, 2010 - Comments: 0

By David Lammers The trends towards vertical transistors, non-silicon channel materials, and resistive RAMs promise to hold center stage at the 2010 IEEE International Electron Devices Meeting (IEDM), set to begin Dec. 6 in San Francisco, Calif. (www.ieee-iedm.org) Taiwan Semiconductor Manufacturing Co. (TSMC, Hsinchu, Taiwan) will present a 22/20nm technology platform based on a FinFET arc... » read more

Betting On 3D
By Ed Sperling - 26 Aug, 2010 - Comments: 0

The continuation of Moore’s Law appears less in doubt than ever. Companies such as Intel, ST, AMD (via GlobalFoundries) and IBM are testing FinFETS and ETSOI and work is being done on the back end to ensure that these new structures can be manufactured with sufficient yield. What’s changed, though, is the resistance by other companies to the progression of Moore’s Law. There is no long... » read more

Stacked Dies Gain Attention, But So Far Little Traction
By Ed Sperling - 17 Dec, 2009 - Comments: 0

By Ed Sperling For the better part of two decades there has been a steady stream of predictions about the abrupt end of Moore’s Law, but it now appears the formula for doubling the number of transistors on a die every couple years will simply dissipate rather than fall off a cliff. While companies such as Intel and IBM continue to develop road maps that extend their road maps all the wa... » read more

Moore’s Law vs. Low Power
By Ed Sperling - 17 Sep, 2009 - Comments: 0

By Ed Sperling Moore’s Law and low-power engineering are natural-born enemies, and this dissension is becoming more obvious at each new process node as the two forces are pushed closer together. The basic problem is that shrinking transistors and line widths between wires opens up far more real estate on a chip, which encourages chip architects and marketing chiefs at chipmakers to take... » read more

New Tools, New Economics
By Ed Sperling - 27 Mar, 2009 - Comments: 0

The race is on to get new development tools out the door, and starting next month you’ll begin seeing many more of them.   Timing is everything, and these tools have to be ready for the next round of chip development—even if the chips aren’t being designed yet. But given that electronics design has to precede an industry recovery by 6 to 12 months, at the very least, and chips and ot... » read more

Another Brick In The Wall
By Ed Sperling - 19 Feb, 2009 - Comments: 0

The wall is in sight.   Moore’s Law has propelled the semiconductor industry at an amazing velocity since it was first introduced in 1965, and despite some minor changes from 18 months to two years, we have pretty much stayed on course. In the past, most people thought we would hit the wall at 1 micron, and they thought it would happen again at 32nm. The road map appears pretty solid dow... » read more

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