Week In Review: Design, Low Power


ON Semiconductor completed its $946 million acquisition of Quantenna Communications, a San Jose-based company that specializes in Wi-Fi chips and software. Aldec introduced automatic UVM register generation to its Riviera-PRO verification platform. Riviera-PRO can now accept a CSV file or IP-XACT register description as an input and, working at the Register Abstraction Layer (RAL) of UVM, ou... » read more

Why Chips Are Getting Noisier


In the past, designers only had to worry about noise for sensitive analog portions of a design. Digital circuitry was immune. But while noise gets worse at newer process nodes, staying at 28nm does not mean that it can be ignored anymore. With Moore's Law slowing, designs have to do more with less. Margins are being squeezed, additional concurrency is added, and attempts are made to opti... » read more

In-Chip Monitoring Becoming Essential Below 10nm


Rising systemic complexity and more potential interactions in heterogeneous designs is making it much more difficult to ensure a chip, or even a block within a chip, will functioning properly without actually monitoring that behavior in real-time. Continuous and sporadic monitoring have been creeping into designs for the past couple of decades. But it hasn’t always been clear how effective... » read more

Week In Review: Design, Low Power


Tools & IP Cadence introduced the Tensilica Vision Q7 DSP, which provides up to 1.82 TOPS and is specifically optimized for simultaneous localization and mapping (SLAM). The DSP has a very long instruction word (VLIW) SIMD architecture, an enhanced instruction set supporting 8/16/32-bit data types and optional VFPU support for single and half precision, and a number of iDMA enhancements in... » read more

The Growing Uncertainty Of Sign-Off At 7/5nm


Having enough confidence in designs to sign off prior to manufacturing is becoming far more difficult at 7/5nm. It is taking longer due to increasing transistor density, thinner gate oxides, and many more power-related operations that can disrupt signal integrity and impact reliability.  For many years, designers have performed design rule checks as part of physical verification of the desi... » read more

Week In Review: Design, Low Power


ANSYS acquired the assets of DfR Solutions, a developer of automated design reliability analysis software. Founded in 2004 and based in Maryland, DfR's tool translates ECAD and MCAE data into 3D finite element models, automates thermal derating and performs thermal and mechanical analysis of electronics earlier in the design cycle. "ANSYS brings industry-leading electronic simulation capabiliti... » read more

Creating A Roadmap For Hardware Security


The U.S. Department of Defense and private industry consortiums are developing comprehensive and cohesive cybersecurity plans that will serve as blueprints for military, industrial and commercial systems. What is particularly noteworthy in all of these efforts is the focus on semiconductors. While software can be patched, vulnerabilities such as Spectre, Meltdown and Foreshadow need to be de... » read more

Low Power Meets Variability At 7/5nm


Power-related issues are beginning to clash with process variation at 7/5nm, making timing closure more difficult and resulting in re-spins caused by unexpected errors and poor functional yield. Variability is becoming particularly troublesome at advanced nodes, and there are multiple causes of that variability. One of the key ones is the manufacturing process, which can be affected by every... » read more

New Approaches To Security


Different approaches are emerging to identify suspicious behavior and shut down potential breaches before they have a chance to do serious damage. This is becoming particularly important in markets where safety is an issue, and in AI and edge devices where the rapid movement of data is essential. These methods are a significant departure from the traditional way of securing devices through l... » read more

The Growing Challenge Of Thermal Guard-Banding


Guard-banding for heat is becoming more difficult as chips are used across a variety of new and existing applications, forcing chipmakers to architect their way through increasingly complex interactions. Chips are designed to operate at certain temperatures, and it is common practice to develop designs with some margin to ensure correct functionality and performance throughout the operat... » read more

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