tag: National Yang Ming Chiao Tung University

Chip Industry Technical Paper Roundup: Jan. 28
By Linda Christensen - 28 Jan, 2025 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=400 /] Find all technical papers here. » read more

Impact of Extremely Low Temperatures On The 5nm SRAM Array Size and Performance
By Technical Paper Link - 20 Jan, 2025 - Comments: 0

A new technical paper titled "Novel Trade-offs in 5 nm FinFET SRAM Arrays at Extremely Low Temperatures" was published by researchers at University of Stuttgart, IIT Kanpur, National Yang Ming Chiao Tung University, Khalifa University, and TU Munich. Abstract "Complementary metal–oxide–semiconductor (CMOS)-based computing promises drastic improvement in performance at extremely low temp... » read more

Roadmap To Neuromorphic Computing (Collaboration of 27 Universities/Companies)
By Technical Paper Link - 09 Jul, 2024 - Comments: 0

A technical paper titled “Roadmap to Neuromorphic Computing with Emerging Technologies” was published by researchers at University College London, Politecnico di Milano, Purdue University, ETH Zurich and numerous other institutions. Summary: "The roadmap is organized into several thematic sections, outlining current computing challenges, discussing the neuromorphic computing approach, ana... » read more

Chip Industry’s Technical Paper Roundup: Dec 5
By Linda Christensen - 05 Dec, 2023 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=171 /] More ReadingTechnical Paper Library home » read more

GAA NSFETs: ML for Device and Circuit Modeling
By Technical Paper Link - 30 Nov, 2023 - Comments: 0

A new technical paper titled "A Comprehensive Technique Based on Machine Learning for Device and Circuit Modeling of Gate-All-Around Nanosheet Transistors" was published by researchers at National Yang Ming Chiao Tung University. Abstract (excerpt) "Machine learning (ML) is poised to play an important part in advancing the predicting capability in semiconductor device compact modeling domai... » read more

Chip Industry’s Technical Paper Roundup: Mar. 14
By Linda Christensen - 14 Mar, 2023 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=86 /] If you have research papers you are trying to promote, we will review them to see if they are a good fit for our global audience. At a minimum, papers need to be well researched and documented, relevant to the semiconductor ecosystem, and free of marketing bias. There is no cost involved for us ... » read more

Reducing Contact Resistance in Developing Transistors Based On 2D Materials
By Technical Paper Link - 10 Mar, 2023 - Comments: 0

A new technical paper titled "WS2 Transistors with Sulfur Atoms Being Replaced at the Interface: First-Principles Quantum-Transport Study" was published by researchers at National Yang Ming Chiao Tung University. Abstract "Reducing the contact resistance is one of the major challenges in developing transistors based on two-dimensional materials. In this study, we perform first-principles ... » read more

Chip Industry’s Technical Paper Roundup: Feb. 28
By Linda Christensen - 28 Feb, 2023 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=83 /] If you have research papers you are trying to promote, we will review them to see if they are a good fit for our global audience. At a minimum, papers need to be well researched and documented, relevant to the semiconductor ecosystem, and free of marketing bias. There is no cost involved for us ... » read more

Chiplet Placer with Thermal Consideration for 2.5D ICs
By Technical Paper Link - 27 Feb, 2023 - Comments: 0

A new technical paper titled "Chiplet Placement for 2.5D IC with Sequence Pair Based Tree and Thermal Consideration" was published by researchers at National Yang Ming Chiao Tung University (Taiwan). Abstract "This work develops an efficient chiplet placer with thermal consideration for 2.5D ICs. Combining the sequence-pair based tree, branch-and-bound method, and advanced placement/pruning... » read more

Chip Industry’s Technical Paper Roundup: Feb. 14
By Linda Christensen - 14 Feb, 2023 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=80 /] If you have research papers you are trying to promote, we will review them to see if they are a good fit for our global audience. At a minimum, papers need to be well researched and documented, relevant to the semiconductor ecosystem, and free of marketing bias. There is no cost involved for us p... » read more

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