tag: network on chip

SoC Integration Complexity: Size Doesn’t (Always) Matter
By Kurt Shuler - 01 Apr, 2021 - Comments: 2

It’s common when talking about complexity in systems-on-chip (SoCs) to haul out monster examples: application processors, giant AI chips, and the like. Breaking with that tradition, consider an internet of things (IoT) design, which can still challenge engineers with plenty of complexity in architecture and integration. This complexity springs from two drivers: very low power consumption, eve... » read more

The Role Of NoCs In System-Level Services
By Kurt Shuler - 03 Sep, 2020 - Comments: 0

The primary objective of any network-on-chip (NoC) interconnect is to move data around a chip as efficiently as possible with as little impact as possible on design closure while meeting or exceeding key design metrics (PPA, etc.). These networks have become the central nervous system of SoCs and are starting to play a larger role in system-level services like quality of service (QoS), debug, p... » read more

An Automotive Value Chain In Flux
By Kurt Shuler - 01 Jul, 2020 - Comments: 0

When companies view suppliers from inside their specialized niches, it is tempting to imagine the business world will continue as-is, with just minimal improvements each year. But in the automotive value chain, this no longer holds. The rapid pace of innovation around intelligent systems in cars is disrupting the business flow. Back in simpler times, semiconductor companies would work with Tier... » read more

Different Levels Of Interconnects
By Ed Sperling - 17 Jun, 2020 - Comments: 0

The interconnect hierarchy from metal 0 in a semiconductor all the way up to racks of servers. Kurt Shuler, vice president of marketing at Arteris IP, explains why each one is different, and how every level can contribute to latency and performance. » read more

Building Your Own NoC And The Hazards Of (Not) Changing
By Kurt Shuler - 04 Jun, 2020 - Comments: 0

There is a perennial challenge that all R&D organizations face – how much of what we develop is essential to our competitive advantage and how much can be acquired at lower cost and risk rather than built from scratch? It’s easy to believe in the heat of battle that everything we are doing must be crucial. But the world continues to change around us. What was optional yesterday may be e... » read more

Last-Level Cache
By Ed Sperling - 06 Apr, 2020 - Comments: 0

Kurt Shuler, vice president of marketing at Arteris IP, explains how to reduce latency and improve performance with last-level cache in order to avoid sending large amounts of data to external memory, and how to ensure quality of service on a chip by taking into account contention for resources. » read more

CXL Vs. CCIX
By Ed Sperling - 06 Dec, 2019 - Comments: 0

Kurt Shuler, vice president of marketing at ArterisIP, explains how these two standards differ, which one works best where, and what each was designed for. » read more

Power Dissipation Of The Network-On-Chip In A System-on-Chip For MPEG-4 Video Encoding
By Arteris - 04 Dec, 2019 - Comments: 0

An oldie but a goodie: Explains power benefits of NoC technology by characterizing a multi-processor system-on-chip (MPSoC) for MPEG4, AVC/H.264 encoding. Explains NoC power model used to analyze power consumption and dissipation. Includes: Description of multi-processor system-on-chip (MPSoC) for Multi-Processor System-on-Chip (MPSoC) for MPEG4, AVC/H.264 encoding Explanation of N... » read more

Application Driven Network On Chip Architecture Exploration And Refinement For A Complex SoC
By Arteris - 01 Jul, 2019 - Comments: 0

This white paper summarizes the various features a NoC is required to implement to be integrated in modern SoCs, describes a top-down approach based on the progressive refinement of the NoC description from its functional specification (Sect. 4) to its verification (Sect. 8), and it uses use cases to show how to identify bottlenecks and converge towards the NoC implementation. To read more, ... » read more

5G Design Changes
By Ed Sperling - 07 Jun, 2019 - Comments: 0

Mike Fitton, senior director of strategic planning at Achronix, talks with Semiconductor Engineering about the two distinct parts of 5G deployment, how to get a huge amount of data from the core to the edge of a device where it is usable, and how a network on chip can improve the flow of data. » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy