tag: network on chip

Using Machine Learning For Characterizations Of NoC Components
By Arteris - 06 Oct, 2021 - Comments: 0

Modern NoC (Network-on-Chip) is built of complex functional blocks, such as packet switches and protocol converters. PPA (performance/power/area) estimates for these components are highly desirable during early design phases – long before NoC gate level netlist is synthesized. At this stage a NoC component is a soft module, described by a set of architectural parameters, like the bit width of... » read more

NoC Experiences From The Trenches
By Kurt Shuler - 28 Sep, 2021 - Comments: 0

Network-on-chip (NoC) interconnect as an alternative to traditional crossbars is already well-proven, but there are still plenty of design teams on the cusp of a transition or who maybe do not yet see a need for a change. As with a switch to any new technology, the first hurdles are often simply misconceptions. When new users first evaluate any new technology, they often make the mistake of att... » read more

Better Optimization For Many-Core AI Chips
By Richard Oxland - 10 Aug, 2021 - Comments: 0

The rise of massively parallel computing has led to an explosion of silicon complexity, driven by the need to process data for artificial intelligence (AI) and machine learning (ML) applications. This complexity is seen in designs like the Cerebras Wafer Scale Engine (figure 1), a tiled manycore, multiple wafer die with a transistor count into the trillions and nearly a million compute cores. ... » read more

Automotive AI Hardware: A New Breed
By Kurt Shuler - 03 Jun, 2021 - Comments: 0

Arteris IP functional safety manager Stefano Lorenzini recently presented “Automotive Systems-on-Chip (SoCs) with AI/ML and Functional Safety” at the Linley Processor Conference. A main point of the presentation was that conventional wisdom on AI hardware markets is binary. There’s AI in the cloud: Big, power-hungry, general-purpose. And there’s AI at the edge: Small, low power, limited... » read more

Interconnects In A Domain-Specific World
By Brian Bailey - 08 Apr, 2021 - Comments: 0

Moving data around is probably the least interesting aspect of system design, but it is one of three legs that defines the key performance indicators (KPI) for a system. Computation, memory, and interconnect all need to be balanced. Otherwise, resources are wasted and performance is lost. The problem is that the interconnect is rarely seen as a contributor to system functionality. It is seen... » read more

SoC Integration Complexity: Size Doesn’t (Always) Matter
By Kurt Shuler - 01 Apr, 2021 - Comments: 2

It’s common when talking about complexity in systems-on-chip (SoCs) to haul out monster examples: application processors, giant AI chips, and the like. Breaking with that tradition, consider an internet of things (IoT) design, which can still challenge engineers with plenty of complexity in architecture and integration. This complexity springs from two drivers: very low power consumption, eve... » read more

The Role Of NoCs In System-Level Services
By Kurt Shuler - 03 Sep, 2020 - Comments: 0

The primary objective of any network-on-chip (NoC) interconnect is to move data around a chip as efficiently as possible with as little impact as possible on design closure while meeting or exceeding key design metrics (PPA, etc.). These networks have become the central nervous system of SoCs and are starting to play a larger role in system-level services like quality of service (QoS), debug, p... » read more

An Automotive Value Chain In Flux
By Kurt Shuler - 01 Jul, 2020 - Comments: 0

When companies view suppliers from inside their specialized niches, it is tempting to imagine the business world will continue as-is, with just minimal improvements each year. But in the automotive value chain, this no longer holds. The rapid pace of innovation around intelligent systems in cars is disrupting the business flow. Back in simpler times, semiconductor companies would work with Tier... » read more

Different Levels Of Interconnects
By Ed Sperling - 17 Jun, 2020 - Comments: 0

The interconnect hierarchy from metal 0 in a semiconductor all the way up to racks of servers. Kurt Shuler, vice president of marketing at Arteris IP, explains why each one is different, and how every level can contribute to latency and performance. » read more

Building Your Own NoC And The Hazards Of (Not) Changing
By Kurt Shuler - 04 Jun, 2020 - Comments: 0

There is a perennial challenge that all R&D organizations face – how much of what we develop is essential to our competitive advantage and how much can be acquired at lower cost and risk rather than built from scratch? It’s easy to believe in the heat of battle that everything we are doing must be crucial. But the world continues to change around us. What was optional yesterday may be e... » read more

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